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HI-3584ACJMF-15 Datasheet(PDF) 7 Page - Holt Integrated Circuits |
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HI-3584ACJMF-15 Datasheet(HTML) 7 Page - Holt Integrated Circuits |
7 / 16 page DATA TRANSMISSION REPEATER OPERATION HI-3584A-15 MASTER RESET ( ) When ENTX goes high, enabling transmission, the FIFO positions are incremented with the top register loading into the data transmission shift register. Within 2.5 data clocks the first data bit appears at 429DO and . The 31 or 32 bits in the data transmission shift register are presented sequentially to the outputs in the ARINC 429 format with the following timing: ARINC DATA BIT TIME 10 Clocks 80 Clocks DATA BIT TIME 5 Clocks 40 Clocks NULL BIT TIME 5 Clocks 40 Clocks WORD GAP TIME 40 Clocks 320 Clocks The word counter detects when all loaded positions have been transmitted and sets the transmitter ready flag, TX/R, high. Repeater mode of operation allows a data word that has been received by the HI-3584A to be placed directly into the transmitter FIFO. Repeater operation is similar to normal receiver operation. In normal operation, either byte of a received data word may be read from the receiver latches first by use of SEL input. During repeater operation however, the lower byte of the data word must be read first. This is necessary because, as the data is being read, it is also being loaded into transmitter FIFO which is always loaded with the lower byte of the data word first. Signal flow for repeater operation is shown in the Timing Diagrams section. Please refer to the Holt AN-300 Application Note for additional information and recommendations on lightning protection of Holt line drivers and line receivers. On a Master Reset data transmission and reception are immediately terminated, all three FIFOs are cleared as are the FIFO flags at the device pins and in the Status Register. The Control Register is not affected by a Master Reset. 429DO HIGH SPEED LOW SPEED TRANSMITTER PARITY SELF TEST SYSTEM OPERATION The parity generator counts the Ones in the 31-bit word. If control register bit CR12 is set low, the 32nd bit transmitted will make parity odd. If the control bit is, high the parity is even. Setting CR4 to a Zero bypasses the parity generator, and allows 32 bits of data to be transmitted. If control register bit CR5 is set low, the transmitter serial output data are internally connected to each of the two receivers, bypassing the analog interface circuitry. Data is passed unmodi- fied to receiver 1 and inverted to receiver 2. The serial data from the transmitter is always present on the 429DO and outputs regardless of the state of CR5. The two receivers are independent of the transmitter. Therefore, control of data exchanges is strictly at the option of the user. The only restrictions are: 1. The received data will be overwritten if the receiver FIFO is full and at least one location is not retrieved before the next complete ARINC word is received. 2. The transmitter FIFO can store 32 words maximum and ignores attempts to load additional data if full. 429DO The HI-3584A-15 option is similar to the HI-3584A with the excep- tion that it allows an external 15 Kohm resistor to be added in se- ries with each ARINC input without affecting the ARINC input thresholds. This option is especially useful in applications where lightning protection circuitry is also required. Each side of the ARINC bus must be connected through a 15 Kohm series resistor in order for the chip to detect the correct ARINC levels. The typical 10 volt differential signal is translated and input to a window comparator and latch. The comparator levels are set so that with the external 15 Kohm resistors, they are just below the standard 6.5 volt minimum ARINC data threshold and just above the standard 2.5 volt maximum ARINC null threshold. The HI-3584A may be operated at clock frequencies beyond that required for ARINC compliant operation. For operation at Master Clock (CLK) frequencies up to 5MHz, please contact Holt appli- cations engineering. HIGH SPEED OPERATION MR FUNCTIONAL DESCRIPTION (cont.) HI-3584A HOLT INTEGRATED CIRCUITS 7 |
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Similar Description - HI-3584ACJMF-15 |
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