HI-8483

HOLT INTEGRATED CIRCUITS

3

FUNCTIONAL DESCRIPTION

The HI-8483 contains two independent ARINC 429 receive

channels, which take differently encoded ARINC level data

and convert it to serial TTL level data. The HI-8483 provides

two complete analog line receivers and no external

components are required.

Input level-shifting resistor networks allow ARINC input

voltage transients up to +/- 200V without damage to the HI-

8483.

Each channel is identical, featuring symmetrical delays for

better high-speed performance. Input common mode

rejection is excellent and threshold voltage is stable,

independent of supply voltage. Data outputs are TTL and

CMOS compatible.

Two TTL compatible test inputs (TESTA and TESTB) used

to simultaneously test both ARINC channels are available.

They can be used to override the ARINC input data and set

the channel outputs to a known state.

The HI-8483 contains two discrete ARINC 429 receiver

channels. Each channel contains three main sections: a

resistor input network, a window comparator, and a logic

output buffer stage. The first stage provides over-voltage

protection and biases the signal using voltage dividers,

providing excellent input common mode rejection. The

TESTA and TESTB inputs are provided to set the outputs to

a predetermined state for built-in channel test capability. If

the test inputs are not used they should be grounded.

The window comparator section detects data from the input

resistor network. An ARINC “high” state generates a logic

“1” at OUTA and an ARINC “low” state generates a logic “1”

at OUTB. An ARINC “null” state at the inputs forces both

outputs to logic “0”. Threshold and hysteresis voltages are

generated by an on-chip voltage reference to maintain

stable switching characteristics over temperature and

supply voltage variations.

The output stage generates a TTL compatible logic output

capable of driving 3 mA of load.

ARINC LEVELS

The ARINC 429 specification requires the following

detection levels:

ONE

+6.5V to +13V

NULL

+2.5V to -2.5V

ZERO

-6.5V to -13V

The HI-8483 guarantees recognition of these levels with a

common mode voltage with respect to GND less than

±13V for the worst case condition.

STATE

DIFFERENTIAL VOLTAGE

NOISE

The input hysteresis is set to reject voltage level transi-

tions in the undefined region between the maximum

ZERO level and the minimum NULL level and the unde-

fined region between the maximum NULL level and the

minimum ONE level.

Therefore, once a valid input

differential voltage threshold is detected, the outputs will

remain at a valid logic state until a new valid input voltage

is detected.

The noise filter capacitors are optional and are added to

provide extra noise immunity by limiting the bandwidth of

the input signal before it reaches the window comparator

stage. Two capacitors are required for each channel and

they must be of the same value. The suggested capacitor

value for 100KHz operation is 39 pF. For lower data rates,

larger values of capacitance may be used to yield better

noise performance. To get optimum performance, the

following equation can be used to calculate capacitor

value for a specific data rate:

C=

F

Where:

C

is the capacitor value in pF

F is the input frequency 10 KHz <= F <= 150 KHz

FILTER

0

FILTER

00

3.95 x 10

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