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RS7202-20GRNEP Datasheet(PDF) 2 Page - Orister Corporation |
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RS7202-20GRNEP Datasheet(HTML) 2 Page - Orister Corporation |
2 / 7 page Page No. : 2/7 DS‐RS7202‐05 April, 2011 www.Orister.com This integrated circuit can be damaged by ESD. Orister Corporation recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Pin Assignments SOT‐25 PACKAGE PIN CODE (NE) SYMBOL DESCRIPTION 1 VIN Regulator Input Pin 2 GND Ground Pin 3 EN Chip Enable Pin 4 NC No Connection SOT‐25 5 VOUT Regulator Output Pin Ordering Information DEVICE DEVICE CODE RS7202‐XX EE YY Z XX is nominal output voltage (for example, 12 = 1.2V, 20 = 2.0V, 33 = 3.3V, 285 = 2.85V). EE is EN Input Logic, Internal Pull‐Up / Down Resistor : (see EN Functions Table) YY is package & Pin Assignments designator : NE : SOT‐25 Z is Lead Free designator : P: Commercial Standard, Lead (Pb) Free and Phosphorous (P) Free Package G: Green (Halogen Free with Commercial Standard) EN Functions Table EE Code EN Operational State H ON GR L OFF H OFF GP L ON |
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