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ADP121 Datasheet(PDF) 2 Page - Analog Devices |
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ADP121 Datasheet(HTML) 2 Page - Analog Devices |
2 / 7 page CN-0187 Circuit Note Rev. 0| Page 2 of 7 The ADL5502 is a mean-responding (true rms) power detector in combination with an envelope detector to accurately determine the crest factor (CF) of a modulated signal. It can be used in high frequency receiver and transmitter signal chains from 450 MHz to 6 GHz with envelope bandwidths over 10 MHz. The peak-hold function allows the capture of short peaks in the envelope with lower sampling rate ADCs. Total current consumption is only 3 mA @ 3 V. The ADA4891-4 is a high speed, quad, CMOS amplifier that offers high performance at a low cost. Current consumption is only 4.4 mA/amplifier at 3 V. The amplifier features true single- supply capability, with an input voltage range that extends 300 mV below the negative rail. The rail-to-rail output stage enables the output to swing to within 50 mV of each rail, ensuring maximum dynamic range. Low distortion and fast settling time makes it ideal for this application. The AD7266is a dual, 12-bit, high speed, low power, successive approximation ADC that operates from a single 2.7 V to 5.25 V power supply and features sampling rates up to 2 MSPS. The device contains two ADCs, each preceded by a 3-channel multiplexer, and a low noise, wide bandwidth track-and-hold amplifier that can handle input frequencies in excess of 30 MHz. Current consumption is only 3 mA at 3 V. It also contains an internal 2.5 V reference. The circuit operates on a single +3.3 V supply from the ADP121, a low quiescent current, low dropout, linear regulator that operates from 2.3 V to 5.5 V and provides up to 150 mA of output current. The low 135 mV dropout voltage at 150 mA load improves efficiency and allows operation over a wide input voltage range. The low 30 μA of quiescent current at full load makes the ADP121 ideal for battery-operated portable equipment. The ADP121 is available in output voltages ranging from 1.2 V to 3.3 V. The parts are optimized for stable operation with small 1 μF ceramic output capacitors. The ADP121 delivers good transient performance with minimal board area. Short-circuit protection and thermal overload protection circuits prevent damage in adverse conditions. The ADP121 is available in tiny 5-lead TSOT and 4-ball, 0.4 mm pitch halide- free WLCSP packages and utilizes the smallest footprint solution to meet a variety of portable applications. CIRCUIT DESCRIPTION The RF signal being measured is applied to the ADL5502. A single 75 Ω termination resistor at the RF input in parallel with the input impedance of the ADL5502 provides a broadband match of 50 Ω. More precise resistive or reactive matches can be applied for narrow frequency band use (see the RF Input Interfacing section of the ADL5502 data sheet). The internal filter capacitor of the ADL5502 provides averaging in the square domain but leaves some residual ac on the output. Signals with high peak-to-average ratios, such as W-CDMA or CDMA2000, can produce ac residual levels on the ADL5502 VRMS dc output. To reduce the effects of these low frequency components in the waveforms, some additional filtering is required. The internal square-domain filter capacitance of the ADL5502 can be augmented by connecting a CFLTR capacitor between Pin 1 (FLTR) and Pin 2 (VPOS). The ac residual can be reduced further by adding capacitance to the VRMS output. The combination of the internal 100 Ω output resistance and the added output capacitance produces a low-pass filter to reduce output ripple of the VRMS output (see the Selecting the Square-Domain Filter and Output Low-Pass Filter section of the ADL5502 data sheet for more details). To measure the peak of a waveform, the control line (CNTL) must be temporally set to a logic high (reset mode for >1 µs) and then set back to a logic low (peak-hold mode). This allows the ADL5502 to be initialized to a known state. When setting the device to measure peak, peak-hold mode should be toggled for a period in which the input rms power and crest factor (CF) is not likely to change. If the ADL5502 is in peak-hold mode and the CF changes from high to low or the input power changes from high to low, a faulty peak measurement is reported. The ADL5502 simply keeps reporting the highest peak that occurred when the peak- hold mode was activated and the input power or the CF was high. Unless CNTL is reset, the PEAK output does not reflect the new peak in the signal. The ADL5502 is capable of sourcing a VRMS output current of approximately 3 mA. The output current is sourced through the on-chip, 100 Ω series resistor; therefore, any load resistor forms a voltage divider with this on-chip resistance. It is recommended that the ADL5502 VRMS output drive high resistive loads to preserve output swing. If an application requires driving a low resistance load (as well as in cases where increasing the nominal conversion gain is desired), a buffering circuit is necessary. The PEAK output is designed to drive 2 pF loads. It is recommended that the ADL5502 PEAK output drive low capacitive loads to achieve a full output response time. The effects of larger capacitive loads are particularly visible when tracking envelopes during the falling transitions. When the envelope is in a fall transition, the load capacitor discharges through the on-chip load resistance of 1.9 kΩ. If the larger capacitive load is unavoidable, the additional capacitance can be counteracted by putting a shunt resistor to ground on the PEAK output to allow for fast discharge. Such a shunt resistor also makes the ADL5502 run higher current, and it should not be lower than 500 Ω. |
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