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AD6657A Datasheet(PDF) 1 Page - Analog Devices |
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AD6657A Datasheet(HTML) 1 Page - Analog Devices |
1 / 5 page Circuit Note CN-0259 Circuits from the Lab™ reference circuits are engineered and tested for quick and easysystemintegrationto helpsolve today’s analog, mixed-signal, and RF design challenges. For more informationand/orsupport,visit www.analog.com/CN0259. Devices Connected/Referenced AD6657A Quad IF Receiver, 200 MSPS Sampling Rate ADL5565 6.0 GHz Ultrahigh Dynamic Range Differential Amplifier High Performance 65 MHz Bandwidth Quad IF Receiver with Antialiasing Filter and 184.32 MSPS Sampling Rate Rev. B Circuitsfromthe Lab™circuitsfromAnalog Deviceshave been designedandbuiltbyAnalogDevices engineers. Standard engineering practices have been employed in the design and construction of eachcircuit,andtheirfunctionandperformancehavebeentestedandverifiedinalabenvironmentat room temperature. However, you are solely responsible for testing the circuit and determining its suitabilityandapplicabilityforyouruseandapplication.Accordingly,innoeventshallAnalogDevices be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause whatsoeverconnectedtotheuseofanyCircuitsfromtheLabcircuits. (Continuedonlastpage) One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2012 Analog Devices, Inc. All rights reserved. EVALUATION AND DESIGN SUPPORT Design and Integration Files Schematics, Layout Files, Bill of Materials CIRCUIT FUNCTION AND BENEFITS The circuit, shown in Figure 1, is a 65 MHz bandwidth receiver front end based on the ADL5565 ultrahigh dynamic range differential amplifier driver and the 11-bit, 200 MSPS AD6657A quad IF receiver. The fourth-order Butterworth antialiasing filter is optimized based on the performance and interface requirements of the amplifier and IF receiver. The total insertion loss due the filter network and other resistive components is only 2.0 dB. The overall circuit has a bandwidth of 65 MHz, with the low-pass filter having a 1 dB bandwidth of 190 MHz and a 3 dB bandwidth of 210 MHz. The pass-band flatness is 1 dB. The circuit is optimized to process a 65 MHz bandwidth IF signal centered at 140 MHz with a sampling rate of 184.32 MSPS. The SNR and SFDR measured with a 140 MHz analog input across the 65 MHz band are 70.1 dBFS and 80.9 dBc, respectively. 0.1µF 0.1µF 0.1µF 0.1µF ADL5565 G = 6dB 2.2pF 40Ω 40Ω XFMR 1:1 Z ECT 1-1-13M INPUT Z = 50Ω ZI = 200Ω INTERNAL INPUT Z AD6657A 11-BIT 200MSPS IF RECEIVER 7.5pF 110nH 5Ω 5Ω 209Ω 50Ω 249Ω +3.3V +1.8V 1.875dB LOSS 0.125dB LOSS 2.0dB LOSS 6dB GAIN FS 1.75V p-p DIFF FILTER 72nH 110nH 72nH 0.1dB LOSS ANALOG INPUT +4.9dBm AT 10MHz OVERALL GAIN = 3.9dB VCM 110Ω RTADC 110Ω RTADC 0.1µF RKB 15Ω RKB 15Ω RA 20Ω RA 20Ω RADC 2.4kΩ 1.5pF VIP2 VIN2 VIP1 VIN1 Figure 1. Single Channel of Quad IF Receiver Front End (Simplified Schematic: All Connections and Decoupling Not Shown) Gains, Losses, and Signal Levels Measured Values at 10 MHz |
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