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BD45E395 Datasheet(PDF) 10 Page - Rohm |
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BD45E395 Datasheet(HTML) 10 Page - Rohm |
10 / 17 page Datasheet 10/14 TSZ02201-0R7R0G300110-1-2 © 2013 ROHM Co., Ltd. All rights reserved. 23.May.2013 Rev.003 www.rohm.com TSZ22111・15・001 BD45Exxxx-M series BD46Exxxx-M series ●Application Information Explanation of Operation For both the open drain type (Fig.15) and the CMOS output type (Fig.16), the detection and release voltages are used as threshold voltages. When the voltage applied to the VDD pins reaches the applicable threshold voltage, the VOUT terminal voltage switches from either “High” to “Low” or from “Low” to “High”. Because the BD45Exxxx-M series uses an open drain output type, it is necessary to connect a pull-up resistor to VDD or another power supply if needed [The output “High” voltage (VOUT) in this case becomes VDD or the voltage of the other power supply]. Fig.15 (BD45Exxxx-M Type Internal Block Diagram) Fig.16 (BD46Exxxx-M Type Internal Block Diagram) Reference Data Examples of Leading (tPLH) and Falling (tPHL) Output Part Number tPLH[ms] tPHL[µs] BD45E275G-M 50 18 BD46E275G-M 50 18 VDD=2.2V 3.2V VDD=3.2V 2.2V *This data is for reference only. The figures will vary with the application, so please confirm actual operating conditions before use. Timing Waveform Example: The following shows the relationship between the input voltages VDD, the output voltage VOUT and ER terminal when the input power supply voltage VDD is made to sweep up and sweep down (the circuits are those in Fig. 15 and 16). 1 When the power supply is turned on, the output is unstable from after over the operating limit voltage (VOPL) until tPHL. Therefore it is possible that the reset signal is not outputted when the rise time of VDD is faster than tPHL. 2 When VDD is greater than VOPL but less than the reset release voltage (VDET + ∆VDET), the output voltages will switch to Low. 3 If VDD exceeds the reset release voltage (VDET + ∆VDET), the counter timer start and VOUT switches from L to H. 4 When more than the high level voltage is supplied ER terminal, VOUT comes to “L” after tPLH delay time. Therefore, a time when ER terminal is “H” is necessary for 100µsec or more. 5 When the ER terminal switches to Low, the counter timer starts to operate, a delay of tPLH occurs, and VOUT switches from “L” to “H”. 6 If VDD drops below the detection voltage (VDET) when the power supply is powered down or when there is a power supply fluctuation, VOUT switches to L (with a delay of tPHL). 7 The potential difference between the detection voltage and the release voltage is known as the hysteresis width (∆VDET). The system is designed such that the output does not toggle with power supply fluctuations within this hysteresis width, thus, preventing malfunctions due to noise. Timing may change depending on application and use. Please verify and confirm using practical applications. Vref R1 R2 R3 VDD GND Oscillation Circuit Counter Timer Q1 VOUT VDD Reset ER Q2 Q1 Vref R1 R2 R3 VDD GND Oscillation Circuit Counter Timer VOUT Reset ER Fig.17 Timing Waveform VDD VDET+ΔVDET VDET VOPL 0V tPHL ① ② VOUT tPLH tPHL tPLH ③ ④ VOL VOH VDD tPLH tPHL ⑥ ⑤ VEH ER ⑦ |
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