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BD90532EFJ-CE2 Datasheet(PDF) 3 Page - Rohm |
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BD90532EFJ-CE2 Datasheet(HTML) 3 Page - Rohm |
3 / 23 page 3/20 Datasheet Datasheet BD9053xEFJ-C Series TSZ02201-0T1T0AL00010-1-2 © 2012 ROHM Co., Ltd. All rights reserved. 20 .SEP.2012 Rev.002 www.rohm.com TSZ22111・15・001 ●Block operation descriptions ■ Standby The circuit enters the state of standby when the EN pin is set to 0.7V or less. All the circuits, such as internal reference voltage VREF, oscillators OSC, and drivers are turned off during standby, and current consumption of the power supply becomes 0µA(25℃, Typ.). Via the FB pin, the output capacitor is discharged at a resistance of 1k Ω. ■ Start operation The circuit starts operating when EN pin is set to 2.1V or more. A soft start circuit (SOFT START) is integrated to prevent inrush current to the capacitor when starting. The output voltage reaches a set voltage with 1ms(Typ.) while following the startup of the soft start circuit. There is a delay of about 200µsec until the soft starts begins after the EN pin is turned on and the internal logic operation is started. In order to prevent a defective start, the short-circuit protection is not active during startup. ■ Error amplifier and phase compensation The voltage of the output feedback pin(FB) is compared with an internal reference voltage. The voltage corresponding to the difference will be generated, and sent to the PWM comparator which determines the duty ratio of the output. The feedback resistor which determines the output voltage, resistance for compensations, and the capacitor are integrated into the BD9053xEFJ-C series. ■ Oscillator The 2.25MHz(Typ.) internally fixed clock is generated and sent to the slope generation circuit (SLOPE) and to the driver. ■ Light load mode and Forced PWM mode BD90535EFJ-C operates in the light load mode when the MODE pin is set to 0.7V or less. When the output load current is small, the switching operation automatically becomes intermittent in the light load mode. The efficiency at light load improves compared to the Forced PWM mode because the switching loss is suppressed by operating intermittently. The intermittently operating load current level changes depending on the input voltage, inductor value, etc. If the MODE pin is set to 2.1V or more, the chip operates in Forced PWM mode. In the Forced PWM mode, the efficiency at a light load decreases compared with the light load mode. However, because of the fixed frequency switching through the entire load range, noise is more easily countered. ■ Overcurrent detection When in the output stage the current flowing to the Pch FET is 3.0A(Min.) or more, the Pch FET is turned off and the power supply to the output is intercepted. The overcurrent detection is operated every cycle, limits the switching duty, and returns at the next clock cycle. Figure 5. Switching operation at light load mode Figure 6. Switching operation at PWM mode VOUT(10mV/div) SW VOUT(10mV/div) SW |
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