3

FN2950.3

April 26, 2006

Pin Description

SYMBOL

PIN

NO.

TYPE

ACTIVE

LEVEL

DESCRIPTION

RD

1

I

Low

READ: The RD input causes the 82C52 to output data to the data bus (D0-D7). The data output

depends upon the state of the address inputs (A0-A1). CS0 enables the RD input.

WR

2

I

Low

WRITE: The WR input causes data from the data bus (D0-D7) to be input to the 82C52. Addressing

and chip select action is the same as for read operations.

D0-D7

3-10

I/O

High

DATA BITS 0-7: The Data Bus provides eight, three-state input/output lines for the transfer of data,

control and status information between the 82C52 and the CPU. For character formats of less than 8

bits, the corresponding D7, D6 and D5 are considered “don't cares” for data WRITE operations and

are 0 for data READ operations. These lines are normally in a high impedance state except during

read operations. D0 is the Least Significant Bit (LSB) and is the first serial data bit to be received or

transmitted.

A0, A1

11, 12

I

High

ADDRESS INPUTS: The address lines select the various internal registers during CPU bus

operations.

IX, OX

13, 14

I/O

CRYSTAL/CLOCK: Crystal connections for the internal Baud Rate Generator. IX can also be used

as an external clock input in which case OX should be left open.

SDO

15

O

High

SERIAL DATA OUTPUT: Serial data output from the 82C52 transmitter circuitry. A Mark (1) is a logic

one (high) and Space (0) is logic zero (low). SD0 is held in the Mark condition when CTS is false,

when RST is true, when the Transmitter Register is empty, or when in the Loop Mode.

GND

16

Low

GROUND: Power supply ground connection.

CTS

17

I

Low

CLEAR TO SEND: The logical state of the CTS line is reflected in the CTS bit of the Modem Status

Register. Any change of state in CTS causes INTR to be set true when INTEN and MIEN are true. A

false level on CTS will inhibit transmission of data on the SD0 output and will hold SD0 in the Mark

(high) state. If CTS goes false during transmission, the current character being transmitted will be

completed. CTS does not affect Loop Mode operation.

DSR

18

I

Low

DATA SET READY: The logical state of the DSR line is reflected in the Modem Status Register. Any

change of state of DSR will cause INTR to be set if INTEN and MIEN are true. The state of this signal

does not affect any other circuitry within the 82C52.

DTR

19

O

Low

DATA TERMINAL READY: The DTR signal can be set (low) by writing a logic 1 to the appropriate bit

in the Modem Control Register (MCR). This signal is cleared (high) by writing a logic 0 in the DTR bit

in the MCR or whenever a reset (RST = high) is applied to the 82C52.

RTS

20

O

Low

REQUEST TO SEND: The RTS signal can be set (low) by writing a logic 1 to the appropriate bit in

the MCR. This signal is cleared (high) by writing a logic 0 to the RTS bit in the MCR or whenever a

reset (RST = high) is applied to the 82C52.

CO

21

O

CLOCK OUT: This output is user programmable to provide either a buffered IX output or a buffered

Baud Rate Generator (16X) clock output. The buffered IX (Crystal or external clock source) output is

provided when the Baud Rate Select Register (BRSR) bit 7 is set to a zero. Writing a logic one to

BRSR bit 7 causes the CO output to provide a buffered version of the internal Baud Rate Generator

clock which operates at sixteen times the programmed baud rate. On reset D7 (CO select) is reset to

0.

TBRE

22

O

High

TRANSMITTER BUFFER REGISTER EMPTY: The TBRE output is set (high) whenever the

Transmitter Buffer Register (TBR) has transferred its data to the Transmit Register. Application of a

reset (RST) to the 82C52 will also set the TBRE output. TBRE is cleared (low) whenever data is

written to the TBR.

RST

23

I

High

RESET: The RST input forces the 82C52 into an “Idle” mode in which all serial data activities are

suspended. The Modem Control Register (MCR) along with its associated outputs are cleared. The

UART Status Register (USR) is cleared except for the TBRE and TC bits, which are set. The 82C52

remains in an “Idle” state until programmed to resume serial data activities. The RST input is a

Schmitt triggered input.

INTR

24

O

High

INTERRUPT REQUEST: The INTR output is enabled by the INTEN bit in the Modem Control

Register (MCR). The MIEN bit selectively enables modem status changes to provide an input to the

INTR logic. Figure 9 in Design Information shows the overall relationship of these interrupt control

signals.

82C52

82C52