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ISL6217ACVZA Datasheet(PDF) 5 Page - Intersil Corporation |
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ISL6217ACVZA Datasheet(HTML) 5 Page - Intersil Corporation |
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5 / 20 page  5 FN9107.3 June 30, 2005 Functional Pin Description VDD - This pin is used to connect +5V to the IC to supply all power necessary to operate the chip. The IC starts to operate when the voltage on this pin exceeds the rising POR threshold and shuts down when the voltage on this pin drops below the falling POR threshold. DACOUT - This pin provides access to the output of the Digital-to-Analog Converter. DSV - The voltage on this pin provides the set point for output voltage during Deep Sleep Mode of operation. FSET - A resistor from this pin to ground programs the switching frequency. PWRCH - This pin selects the number of power channels. A HIGH logic level on this pin enables 2 channel operation, and a LOW logic signal enables single channel operation. EN - This pin is connected to the system signal VR_ON and provides the enable/disable function for the PWM controller. DRSEN - This pin connects to system logic “DPRSLPVR” and enables Deeper Sleep mode of operation when a logic HIGH is detected on this pin. DSEN# - This pin connects to system logic “STP_CPU#” and enables Deep Sleep mode of operation. Deep Sleep is enabled when a logic LOW signal is detected on this pin. VID0, VID1, VID2, VID3, VID4, VID5 - These pins are used as inputs to the 6-bit Digital-to-Analog converter (DAC). VID0 is the least significant bit and VID5 is the most significant bit. PGOOD - This pin is used as an input and an output and is tied to the Vccp and Vcc_mch PGOOD signals. During start- up, this pin is recognized as an input and prevents further slewing of the output voltage from the “Boot” level until PGOOD from Vccp and Vcc_mch is enabled High. After Start-up, this pin has an open drain output used to indicate the status of the CORE output voltage. This pin is pulled low when the system output is outside of the regulation limits. PGOOD includes a timer for power-on delay. EA+ - This pin is connected to the non-inverting input of the error amplifier and is used for setting the “Droop” voltage. COMP - This pin provides connection to the error amplifier output. FB - This pin is connected to the inverting input of the error amplifier. SOFT - This pin programs the slew rate of VID changes, Deep Sleep and Deeper Sleep transitions and Soft-Start after initializing. This pin is connected to ground via a capacitor, and to EA+ through an external “Droop” resistor. VBAT - Voltage on this pin provides feed-forward battery information which adjusts the oscillator ramp amplitude. ISEN1, ISEN2 - These pins are used as current sense inputs from the individual converter channel phase nodes. PHASE1, PHASE2 - These pins are connected to the phase nodes of channels 1 and 2, respectively. UG1, UG2 - These pins are the gate-drive outputs to the high side MOSFETs for channels 1 and 2, respectively. BOOT1, BOOT2 - These pins are connected to the bootstrap capacitors, for upper gate-drive, for channels 1 and 2, respectively. VSSP1, VSSP2 - These pins are connected to the power ground of channels 1 and 2, respectively. LG1, LG2 - These pins are the gate-drive outputs to the low side MOSFETs for channels 1 and 2, respectively. VDDP - This pin provides a low-esr bypass connection to the internal gate drivers for the +5V source. VSEN - This pin is used for remote sensing of the microprocessor CORE voltage. DRSV - The voltage on this pin provides the set point for output voltage during Deeper Sleep Mode of operation. OCSET - A resistor from this pin to ground sets the overcurrent protection threshold. The current from this pin should be between 10µA and 25µA (70k Ω - 175kΩ equivalent) pull-down resistance. STV - The voltage on this pin sets the initial Start-Up or “Boot” voltage. VSS - This pin provides connection for signal ground. ISL6217A |
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