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X40031VC Datasheet(PDF) 9 Page - Intersil Corporation |
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X40031VC Datasheet(HTML) 9 Page - Intersil Corporation |
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9 / 23 page  9 FN8114.2 August 25, 2008 The new VTRIPX voltage to be applied to VXMON will now be: VTRIPX (desired) – (VTRIPX (actual) – VTRIPX (desired)). Note: This operation does not corrupt the memory array. Setting a Lower VTRIPx Voltage (x=1, 2, 3) In order to set VTRIPx to a lower voltage than the present value, then VTRIPx must first be “reset” according to the procedure described in the following. Once VTRIPx has been “reset”, then VTRIPx can be set to the desired voltage using the procedure described in “Setting a Higher VTRIPx Voltage (x = 1, 2, 3)” on page 8. Resetting the VTRIPx Voltage To reset a VTRIPx voltage, apply the programming voltage (Vp) to the WDO pin before a START condition is set up on SDA. Next, issue on the SDA pin the Slave Address A0h followed by the Byte Address 03h for VTRIP1, 0Bh for VTRIP2, and 0Fh for VTRIP3, followed by 00h for the Data Byte in order to reset VTRIPx. The STOP bit following a valid write operation initiates the programming sequence. Pin WDO must then be brought LOW to complete the operation. After being reset, the value of VTRIPx becomes a nominal value of 1.7V or lesser. Note: This operation does not corrupt the memory array. Set VCC ≅ 1.5(V2MON or V3MON), when setting VTRIP2 or VTRIP3 respectively. Control Register The Control Register provides the user a mechanism for changing the Block Lock and Watchdog Timer settings. The Block Lock and Watchdog Timer bits are nonvolatile and do not change when power is removed. The Control Register is accessed with a special preamble in the slave byte (1011) and is located at address 1FFh. It can only be modified by performing a byte write operation directly to the address of the register and only one data byte is allowed for each register write operation. Prior to writing to the Control Register, the WEL and RWEL bits must be set using a two step process, with the whole sequence requiring 3 steps. See “Writing to the Control Registers” on page 11. The user must issue a stop, after sending this byte to the register, to initiate the nonvolatile cycle that stores WD1, WD0, PUP1, PUP0 and BP. The X40030, X40031, X40034, X40035 will not acknowledge any data bytes written after the first byte is entered. The state of the Control Register can be read at any time by performing a random read at address 1FFh, using the special preamble. Only one byte is read by each register read operation. The master should supply a stop condition to be consistent with the bus protocol. RWEL: Register Write Enable Latch (Volatile) The RWEL bit must be set to “1” prior to a write to the Control Register. FIGURE 5. SAMPLE VTRIP RESET CIRCUIT 7 6 543 21 0 PUP1 WD1 WD0 BP 0 RWEL WEL PUP0 1 6 2 7 14 13 9 8 X40030 VTRIP1 ADJ. VP SDA SCL µC ADJUST RUN V2FAIL VTRIP2 ADJ. RESET X40030, X40031, X40034, X40035 |
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