Integrated Silicon Solution, Inc. — 1-800-379-4774

11

Rev. N

02/12/2010

IS61VPS25672A,IS61LPS25672A

IS61VPS51236A, IS61LPS51236A, IS61VPS102418A, IS61LPS102418A

OPERATION

ADDRESS

CE

CE

CE

CE

CE

CE2

CE2

CE2

CE2

CE2

CE2

ZZ

ADSP

ADSP

ADSP

ADSP

ADSP ADSC

ADSC

ADSC

ADSC

ADSC

ADV

ADV

ADV

ADV

ADV WRITE

WRITE

WRITE

WRITE

WRITE

OE

OE

OE

OE

OE

CLK

DQ

Deselect Cycle, Power-Down

None

H

X

X

L

X

L

X

X

X

L-H

High-Z

Deselect Cycle, Power-Down

None

L

X

L

L

L

XXXX

L-H

High-Z

Deselect Cycle, Power-Down

None

L

H

X

L

L

XXXX

L-H

High-Z

Deselect Cycle, Power-Down

None

L

X

L

L

H

L

X

X

X

L-H

High-Z

Deselect Cycle, Power-Down

None

L

H

X

L

H

L

X

X

X

L-H

High-Z

Snooze Mode, Power-Down

None

X

X

X

H

XXXXXX

High-Z

Read Cycle, Begin Burst

External

L

L

H

L

L

X

X

X

L

L-H

Q

Read Cycle, Begin Burst

External

L

L

H

L

L

X

X

X

H

L-H

High-Z

Write Cycle, Begin Burst

External

L

L

H

L

H

L

X

L

X

L-H

D

Read Cycle, Begin Burst

External

L

L

H

L

H

L

X

H

L

L-H

Q

Read Cycle, Begin Burst

External

L

L

H

L

H

L

X

H

H

L-H

High-Z

Read Cycle, Continue Burst

Next

X

X

X

L

H

H

L

H

L

L-H

Q

Read Cycle, Continue Burst

Next

X

X

X

L

H

H

L

H

H

L-H

High-Z

Read Cycle, Continue Burst

Next

H

X

X

L

X

H

L

H

L

L-H

Q

Read Cycle, Continue Burst

Next

H

X

X

L

X

H

L

H

H

L-H

High-Z

Write Cycle, Continue Burst

Next

X

X

X

L

H

H

L

L

X

L-H

D

Write Cycle, Continue Burst

Next

H

X

X

L

X

H

L

L

X

L-H

D

Read Cycle, Suspend Burst

Current

X

X

X

L

HHHH

L

L-H

Q

Read Cycle, Suspend Burst

Current

X

X

X

L

HHHHH

L-H

High-Z

Read Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

H

L

L-H

Q

Read Cycle, Suspend Burst

Current

H

X

X

L

X

HHHH

L-H

High-Z

Write Cycle, Suspend Burst

Current

X

X

X

L

H

H

H

L

X

L-H

D

Write Cycle, Suspend Burst

Current

H

X

X

L

X

H

H

L

X

L-H

D

NOTE:

1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.

2. For

WRITE, L means one or more byte write enable signals (BWa-h) and BWE are LOW or GW is LOW. WRITE = H for all

BWx, BWE, GW HIGH.

3.

BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and

DQPc.

BWd enables WRITEs to DQd’s and DQPd. BWe enables WRITEs to DQe’s and DQPe. BWf enables WRITEs to DQf’s

and DQPf.

BWg enables WRITEs to DQg’s and DQPg. BWh enables WRITEs to DQh’s and DQPh. DQPa-DQPh are avail-

able on the x72 version. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version.

4. All inputs except

OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

5. Wait states are inserted by suspending burst.

6. For a WRITE operation following a READ operation,

OE must be HIGH before the input data setup time and held HIGH during the

input data hold time.

7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.

8.

ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write

enable signals and

BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.