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IS65WV102416BLL-25MA3 Datasheet(PDF) 11 Page - Integrated Silicon Solution, Inc |
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IS65WV102416BLL-25MA3 Datasheet(HTML) 11 Page - Integrated Silicon Solution, Inc |
11 / 17 page Integrated Silicon Solution, Inc. — www.issi.com 11 Rev. A 01/18/08 IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL Notes: 1. WRITEisaninternallygeneratedsignalassertedduringanoverlapoftheLOWstatesonthe CS1,CS2andWEinputsandatleastoneoftheLBandUBinputs beingintheLOWstate. 2. WRITE = ( CS1)[(LB)=(UB)](WE). AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW) DATA-IN VALID DATA UNDEFINED tWC tSCS1 tSCS2 tAW tHA tPWE tHZWE HIGH-Z tLZWE tSA tSD tHD ADDRESS CS1 CS2 WE DOUT DIN LB, UB tPWB WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range) 25ns 35 ns Symbol Parameter Min. Max. Min. Max. Unit tWC Write Cycle Time 25 — 35 — ns tSCS1/tSCS2 CS1/CS2 to Write End 18 — 25 — ns tAW Address Setup Time to Write End 15 — 25 — ns tHA Address Hold from Write End 0 — 0 — ns tSA Address Setup Time 0 — 0 — ns tPWB LB, UB Valid to End of Write 18 — 25 — ns tPWE(4) WE Pulse Width 18 — 30 — ns tSD Data Setup to Write End 12 — 15 — ns tHD Data Hold from Write End 0 — 0 — ns tHZWE(3) WE LOW to High-Z Output — 12 — 20 ns tLZWE(3) WE HIGH to Low-Z Output 5 — 5 — ns Notes: 1. Testconditionsassumesignaltransitiontimesof5nsorless,timingreferencelevelsof0.9V/1.5V,inputpulselevelsof 0.4toVDD-0.2V/0.4VtoVDD-0.3Vand outputloadingspecifiedinFigure1. 2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested. 4. tPWE > tHZWE + tSD when OE is LOW. |
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