Integrated Silicon Solution, Inc. — www.issi.com

11

Rev. A

01/18/08

IS62WV102416ALL

IS62WV102416BLL

IS65WV102416BLL

Notes:

1. WRITEisaninternallygeneratedsignalassertedduringanoverlapoftheLOWstatesonthe

CS1,CS2andWEinputsandatleastoneoftheLBandUBinputs

beingintheLOWstate.

2. WRITE = (

CS1)[(LB)=(UB)](WE).

AC WAVEFORMS

DATA-IN VALID

DATA UNDEFINED

HIGH-Z

ADDRESS

CS1

CS2

WE

DOUT

DIN

LB, UB

25ns

35 ns

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

Write Cycle Time

25

—

35

—

ns

18

—

25

—

ns

Address Setup Time to Write End

15

—

25

—

ns

Address Hold from Write End

0

—

0

—

ns

Address Setup Time

0

—

0

—

ns

LB, UB Valid to End of Write

18

—

25

—

ns

WE Pulse Width

18

—

30

—

ns

Data Setup to Write End

12

—

15

—

ns

Data Hold from Write End

0

—

0

—

ns

WE LOW to High-Z Output

—

12

—

20

ns

WE HIGH to Low-Z Output

5

—

5

—

ns

Notes:

outputloadingspecifiedinFigure1.

2. The internal write time is defined by the overlap of

CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but

any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the

write.

3. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.

OE is LOW.