Virtex-6 Family Overview

DS150 (v2.4) January 19, 2012

www.xilinx.com

Product Specification

7

Input/Output

The number of I/O pins varies from 240 to 1200 depending on device and package size. Each I/O pin is configurable and can

comply with a large number of standards, using up to 2.5V. The Virtex-6 FPGA SelectIO Resources User Guide describes

the I/O compatibilities of the various I/O options. With the exception of supply pins and a few dedicated configuration pins,

all other package pins have the same I/O capabilities, constrained only by certain banking rules.

which also powers certain input buffers. Some single-ended input buffers require an externally applied reference voltage

value.

I/O Electrical Characteristics

ground, and can be put into high-Z state. The system designer can specify the slew rate and the output strength. The input

is always active but is usually ignored while the output is active. Each pin can optionally have a weak pull-up or a weak pull-

down resistor.

Any signal pin pair can be configured as differential input pair or output pair. Differential input pin pairs can optionally be

terminated with a 100

Ωinternal resistor. All Virtex-6 devices support differential standards beyond LVDS: HT, RSDS, BLVDS,

differential SSTL, and differential HSTL.

Digitally Controlled Impedance

Digitally controlled impedance (DCI) can control the output drive impedance (series termination) or can provide parallel

connected to ground. The resistor must be either 1× or 2× the characteristic trace impedance, typically close to 50

Ω.

I/O Logic

Input and Output Delay

This section describes the available logic resources connected to the I/O interfaces. All inputs and outputs can be configured

as either combinatorial or registered. Double data rate (DDR) is supported by all inputs and outputs. Any input or output can

be individually delayed by up to 32 increments of ~78 ps each. This is implemented as IODELAY. The number of delay steps

can be set by configuration and can also be incremented or decremented while in use.

For using either IODELAY, the system designer must instantiate the IODELAY control block and clock it with a frequency

close to 200 MHz. Each 32-tap total IODELAY is controlled by that frequency, thus unaffected by temperature, supply

voltage, and processing variations.

ISERDES and OSERDES

Many applications combine high-speed bit-serial I/O with slower parallel operation inside the device. This requires a

serializer and deserializer (SerDes) inside the I/O structure. Each input has access to its own deserializer (serial-to-parallel

converter) with programmable parallel width of 2, 3, 4, 5, 6, 7, 8, or 10 bits. Each output has access to its own serializer

(parallel-to-serial converter) with programmable parallel width of up to 8 bits wide for single data rate (SDR), or up to 10 bits

wide for double data rate (DDR).

System Monitor

Every Virtex-6 FPGA contains a System Monitor circuit providing thermal and power supply status information. Sensor

outputs are digitized by a 10-bit 200kSPS analog-to-digital converter (ADC). This fully tested and specified ADC can also be

used to digitize up to 17 external analog input channels. The System Monitor ADC utilizes an on-chip reference circuit

thereby eliminating the need for any external active components. On-chip temperature and power supplies are monitored

with a measurement accuracy of ±4°C and ±1% respectively.

By default the System Monitor continuously digitizes the output of all on-chip sensors. The most recent measurement results

together with maximum and minimum readings are stored in dedicated registers for access at any time through the DRP or

JTAG interfaces. User defined alarm thresholds can automatically indicate over temperature events and unacceptable power

supply variation. A specified limit (for example: 125°C) can be used to initiate an automatic power down.