Rev. 1.0 / Nov. 2012

10

ROW AND COLUMN ADDRESS TABLE

4Gb

Note1: Page size is the number of bytes of data delivered from the array to the internal sense amplifiers



when an ACTIVE command is registered. Page size is per bank, calculated as follows:

 8

where COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits

Configuration

1Gb x 4

512Mb x 8

256Mb x 16

# of Banks

8

8

8

Bank Address

BA0 - BA2

BA0 - BA2

BA0 - BA2

Auto precharge

A10/AP

A10/AP

A10/AP

BL switch on the fly

A12/BC

A12/BC

A12/BC

Row Address

A0 - A15

A0 - A15

A0 - A14

Column Address

A0 - A9,A11

A0 - A9

A0 - A9

1 KB

1 KB

2 KB