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FL103M Datasheet(PDF) 4 Page - Fairchild Semiconductor

Part # FL103M
Description  Design Guideline for LED Lamp Control Using Primary-Side Regulated Flyback Converter, FL103M
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FL103M Datasheet(HTML) 4 Page - Fairchild Semiconductor

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AN-9741
APPLICATION NOTE
© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
Rev. 1.0.0 • 6/27/11
4
2
1
T
T
D
ch
=
Figure 5. DC Link Voltage Waveforms
The maximum DC link voltage is given as:
max
max
2
LINE
DL
V
V
×
=
(14)
where VLINE
max is the maximum line voltage.
The minimum input DC link voltage at 50% nominal output
voltage is given as:
L
DL
ch
B
IN
LINE
B
DL
f
C
D
P
V
V
×
×
=
)
1
(
)
(
2
@
2
min
min
@
(15)
The minimum input DC link voltage at minimum output
voltage are given as:
L
DL
ch
C
IN
LINE
C
DL
f
C
D
P
V
V
×
×
=
)
1
(
)
(
2
@
2
min
min
@
(16)
[STEP-3] Determine Transformer Turns Ratio
Figure 6 shows the MOSFET drain-to-source voltage
waveforms. When the MOSFET is turned off, the sum of
the input voltage (VDL) and the output voltage reflected to
the primary is imposed across the MOSFET as:
RO
DL
nom
DS
V
V
V
+
=
max
(17)
where VRO is reflected output voltage defined as:
(
)
F
O
P
S
RO
V
V
N
N
V
+
×
=
(18)
where VF is the diode forward voltage drop and NP and NS
are number of turns for the primary side and secondary
side, respectively.
When the MOSFET is turned on; the output voltage,
together with input voltage reflected to the secondary, are
imposed across the diode as:
max
DL
P
S
O
F
V
N
N
V
V
×
+
=
(19)
As observed in Equations (5) and (6), increasing the
transformer turns ratio (NP/NS) results in increased voltage
of MOSFET, while it leads to reduced voltage stress of
rectifier diode. Therefore, the transformer turns ratio
(NP/NS) should be determined by the compromise between
MOSFET and diode voltage stresses. When determining the
transformer turns ratio, the voltage overshoot (VOS) on drain
voltage should be also considered. The maximum voltage
stress of MOSFET is given as:
OS
RO
DL
DS
V
V
V
V
+
+
=
max
max
(20)
For reasonable snubber design, voltage overshoot (VOS) is
typically 1~1.5 times the reflected output voltage. It is also
typical to have a margin of 15~20% of breakdown voltage
for maximum MOSFET voltage stress.
S
P
F
O
N
N
V
V
×
+
)
(
Figure 6. Voltage Stress of MOSFET
The transformer turns ratio between the auxiliary winding
and secondary winding (NA/NS) should be determined by
considering the permissible IC supply voltage (VDD) range
and minimum output voltage in constant current. When the
LED operates in constant current, VDD is changed, together
with the output voltage, as seen Figure 7. The overshoot of
auxiliary winding voltage caused by the leakage inductance
also affects the VDD. At light-load condition, where the
overshoot of auxiliary winding voltage is negligible, VDD
voltage is given as:
(
)
FA
F
O
S
A
DD
V
V
V
N
N
V
+
×
=
1
min
(21)
The actual VDD voltage at heavy load is higher than
Equation (21) due to the overshoot by the leakage
inductance, which is proportional to the voltage overshoot
of MOSFET drain-to-source voltage shown in Figure 7.
Considering the effect of voltage overshoot, the VDD
voltages for nominal output voltage and minimum output
voltage are given as:
FA
OS
P
S
F
O
S
A
DD
V
V
N
N
V
V
N
N
V


×
+
+
×
max
(22)
FA
OS
P
S
F
O
S
A
DD
V
V
N
N
V
V
N
N
V


×
+
+
×
min
2
min
(23)
where VFA is the diode forward-voltage drop of auxiliary
winding diode.


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