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HMT41GS6AFR8C-PB Datasheet(PDF) 5 Page - Hynix Semiconductor |
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HMT41GS6AFR8C-PB Datasheet(HTML) 5 Page - Hynix Semiconductor |
5 / 55 page Rev. 1.0 / Jul. 2013 5 Pin Descriptions Pin Name Description Num ber Pin Name Description Num ber CK[1:0] Clock Input, positive line 2 DQ[63:0] Data Input/Output 64 CK[1:0] Clock Input, negative line 2 DM[7:0] Data Masks 8 CKE[1:0] Clock Enables 2 DQS[7:0] Data strobes 8 RAS Row Address Strobe 1 DQS[7:0] Data strobes, negative line 8 CAS Column Address Strobe 1 EVENT Temperature event pin 1 WE Write Enable 1 TEST Logic Analyzer specific test pin (No connect on SODIMM) 1 S[1:0] Chip Selects 2 RESET Reset Pin 1 A[9:0],A11, A[15:13] Address Inputs 14 VDD Core and I/O Power 18 A10/AP Address Input/Autoprecharge 1 VSS Ground 52 A12/BC Address Input/Burst chop 1 BA[2:0] SDRAM Bank Addresses 3 VREFDQ Input/Output Reference 1 ODT[1:0] On Die Termination Inputs 2 VREFCA 1 SCL Serial Presence Detect (SPD) Clock Input 1 VTT Termination Voltage 2 SDA SPD Data Input/Output 1 VDDSPD SPD Power 1 SA[1:0] SPD Address Inputs 2 NC Reserved for future use 2 Total: 204 |
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