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HMT41GR7AFR4C-H9 Datasheet(PDF) 4 Page - Hynix Semiconductor |
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HMT41GR7AFR4C-H9 Datasheet(HTML) 4 Page - Hynix Semiconductor |
4 / 71 page Rev. 0.1 / Jul. 2012 4 Key Parameters *SK hynix DRAM devices support optional downbinning to CL11, CL9 and CL7. SPD setting is programmed to match. Speed Grade Address Table MT/s Grade tCK (ns) CAS Latency (tCK) tRCD (ns) tRP (ns) tRAS (ns) tRC (ns) CL-tRCD-tRP DDR3-1066 -G7 1.875 7 13.125 13.125 37.5 50.625 7-7-7 DDR3-1333 -H9 1.5 9 13.5 (13.125)* 13.5 (13.125)* 36 49.5 (49.125)* 9-9-9 DDR3-1600 -PB 1.25 11 13.75 (13.125)* 13.75 (13.125)* 35 48.75 (48.125)* 11-11-11 DDR3-1866 -Rd 1.07 13 13.91 (13.125)* 13.91 (13.125)* 34 47.91 (48.125)* 13-13-13 Grade Frequency [MHz] Remark CL6 CL7 CL8 CL9 CL10 CL11 CL12 CL13 -G7 800 1066 1066 -H9 800 1066 1066 1333 1333 -PB 800 1066 1066 1333 1333 1600 -RD 800 1066 1066 1333 1333 1600 1866 4GB(1Rx8) 8GB(1Rx4) 8GB(2Rx8) 16GB(2Rx4) 32GB(4Rx4) Refresh Method 8K/64ms 8K/64ms 8K/64ms 8K/64ms 8K/64ms Row Address A0-A15 A0-A15 A0-A15 A0-A15 A0-A15 Column Address A0-A9 A0-A9,A11 A0-A9 A0-A9,A11 A0-A9,A11 Bank Address BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2 Page Size 1KB 1KB 1KB 1KB 1KB |
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