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WRITEVAR16 Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc |
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WRITEVAR16 Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc |
6 / 36 page MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2 6 Freescale Semiconductor Pin Descriptions Pin Descriptions Table 2 is a pin-by-pin functional description of the MC3PHAC. The pin numbers in the table refer to the 28-pin packages (see Figure 2). Table 2. MC3PHAC Pin Descriptions (Sheet 1 of 2) Pin Number Pin Name Pin Function 1VREF Reference voltage input for the on-chip ADC. For best signal-to-noise performance, this pin should be tied to VDDA (analog). 2 RESET A logic 0 on this pin forces the MC3PHAC to its initial startup state. All PWM outputs are placed in a high-impedance mode. Reset is a bidirectional pin, allowing a reset of the entire system. It is driven low when an internal reset source is asserted (for example, loss of clock or low VDD). 3VDDA Provides power for the analog portions of the MC3PHAC, which include the internal clock generation circuit (PLL) and the ADC 4VSSA Returns power for the analog portions of the MC3PHAC, which include the internal clock generation circuit (PLL) and the ADC 5OSC2 Oscillator output used as part of a crystal or ceramic resonator clock circuit.(1) 6OSC1 Oscillator input used as part of a crystal or ceramic resonator clock circuit. Can also accept a signal from an external canned oscillator.(1) 7PLLCAP A capacitor from this pin to ground affects the stability and reaction time of the PLL clock circuit. Smaller values result in faster tracking of the reference frequency. Larger values result in better stability. A value of 0.1 µF is typical. 8 PWMPOL_BASEFREQ Input which is sampled at specific moments during initialization to determine the PWM polarity and the base frequency (50 or 60 Hz) 9 PWM_U_TOP PWM output signal for the top transistor driving motor phase U 10 PWM_U_BOT PWM output signal for the bottom transistor driving motor phase U 11 PWM_V_TOP PWM output signal for the top transistor driving motor phase V 12 PWM_V_BOT PWM output signal for the bottom transistor driving motor phase V 13 PWM_W_TOP PWM output signal for the top transistor driving motor phase W 14 PWM_W_BOT PWM output signal for the bottom transistor driving motor phase W 15 FAULTIN A logic high on this input will immediately disable the PWM outputs. A retry timeout interval will be initiated once this pin returns to a logic low state. 16 PWMFREQ_RxD In standalone mode, this pin is an output that drives low to indicate the parameter mux input pin is reading an analog voltage to specify the desired PWM frequency. In PC master software mode, this pin is an input which receives UART serial data. |
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