11

Notes:

1. This is the maximum voltage that can be applied across the

Differential Transmitter Data Inputs to prevent damage to the input

ESD protection circuit.

3. The specified signaling rate of 10 MBd to 125 MBd guarantees

operation of the transmitter and receiver link to the full conditions

listed in the FDDI Physical Layer Medium Dependent standard.

Specifically, the link bit-error-ratio will be equal to or better than

of the link is capable of DC to 125 MBd. The receiver is internally

AC-coupled which limits the lower signaling rate to 10 MBd. For

purposes of definition, the symbol rate (Baud), also called signaling

rate, fs, is the reciprocal of the symbol time. Data rate (bits/sec) is

the symbol rate divided by the encoding factor used to encode the

data (symbols/bit).

4. The power supply current needed to operate the transmitter is

provided to differential ECL circuitry. This circuitry maintains a nearly

constant current flow from the power supply. Constant current

operation helps to prevent unwanted electrical noise from being

generated and conducted or emitted to neighboring circuitry.

6. This value is measured with the outputs terminated into 50 W

average.

7. The power dissipation value is the power dissipated in the

transmitter and receiver itself. Power dissipation is calculated as the

sum of the products of supply voltage and currents, minus the sum

of the products of the output voltages and currents.

9. The output rise and fall times are measured between 20% and 80%

10. Duty Cycle Distortion contributed by the receiver is measured at

the 50% threshold using an IDLE Line State, 125 MBd (62.5 MHz

square-wave), input signal. The input optical power level is -20 dBm

average. See Application Information–Data Link Jitter Section for

further information.

11. Data Dependent Jitter contributed by the receiver is specified with

the FDDI DDJ test pattern described in the FDDI PMD Annex A.5.

The input optical power level is -20 dBm average. See Application

Information – Data Link Jitter Section for further information.

12. Random Jitter contributed by the receiver is specified with an

IDLE Line State, 125 MBd (62.5 MHz square-wave), input signal.

See Application Information – Data Link Jitter Section for further

information.

13. These optical power values are measured with the following

conditions:

• The Beginning of Life (BOL) to the Endof Life (EOL) optical power

degradation is typically 1.5 dB per the industry convention for

long wavelength LEDs. The actual degradation observed in

Avago Technologie’s 1300 nm LED products is < 1dB, as specified

in this data sheet.

• Over the specified operating voltage and temperature ranges.

• With HALT Line State, (12.5 MHz square-wave), input signal.

• At the end of one meter of noted optical fiber with cladding

modes removed. The average power value can be converted to

a peak power value by adding 3 dB. Higher output optical power

transmitters are available on special request.

14. The Extinction Ratio is a measure of the modulation depth of the

optical signal. The data “0” output optical power is compared to the

data “1” peak output optical power and expressed as a percentage.

With the transmitter driven by a HALT Line State (12.5 MHz

squarewave) signal, the average optical power is measured. The data

“1” peak power is then calculated by adding 3 dB to the measured

average optical power. The data “0” output optical power is found

by measuring the optical power when the transmitter is driven by a

logic“0”input. The extinction ratio is the ratio of the optical power at

the“0”level compared to the optical power at the“1”level expressed

as a percentage or in decibels.

15. The transmitter provides compliance with the need for Transmit_

Disable commands from the FDDI SMT layer by providing an Output

Optical Power level of < -45 dBm average in response to a logic “0”

input. This specification applies to either 62.5/125 μm or 50/125 μm

fiber cables.

16. This parameter complies with the FDDI PMD requirements for the

tradeoffs between center wavelength, spectral width, and rise/fall

times shown in Figure 9.

17. This parameter complies with the optical pulse envelope from the

FDDI PMD shown in Figure 10. The optical rise and fall times are

measured from 10% to 90% when the transmitter is driven by the

FDDI HALT Line State (12.5 MHz square-wave) input signal.

18. Duty Cycle Distortion contributed by the transmitter is measured

at a 50% threshold using an IDLE Line State, 125 MBd (62.5 MHz

square-wave), input signal. See Application Information – Data Link

Jitter Performance Section of this data sheet for further details.

19. Data Dependent Jitter contributed by the transmitter is specified

with the FDDI test pattern described in FDDI PMD Annex A.5. See

Application Information – Data Link Jitter Performance Section of

this data sheet for further details.

20. Random Jitter contributed by the transmitter is specified with an

IDLE Line State, 125 MBd (62.5 MHz square-wave), input signal. See

Application Information – Data Link Jitter Performance Section of

this data sheet for further details.

21. This specification is intended to indicate the performance of the

receiver when Input Optical Power signal characteristics are present

per the following definitions. The Input Optical Power dynamic

range from the minimum level (with a window timewidth) to the

maximum level is the range over which the receiver is guaranteed to

provide output data with a Bit-Error-Ratio (BER) better than or equal

• At the Beginning of Life (BOL).

• Over the specified operating voltage and temperature ranges.

• Input symbol pattern is the FDDI test pattern defined in FDDI

PMD Annex A.5 with 4B/5B NRZI encoded data that contains a

duty-cycle base-line wander effect of 50 kHz. This sequence

causes a near worst-case condition for intersymbol interference.

• Receiver data window time-width is 2.13 ns or greater and

centered at midsymbol. This worst-case window timewidth is

the minimum allowed eyeopening presented to the FDDI PHY

PM_Data indication input (PHY input) per the example in FDDI

PMD Annex E. This minimum window time-width of 2.13 ns is

based upon the worst-case FDDI PMD Active Input Interface

optical conditions for peak-to-peak DCD (1.0 ns), DDJ (1.2 ns) and

RJ (0.76 ns) presented to the receiver.

To test a receiver with the worst-case FDDI PMD Active Input jitter

condition requires exacting control over DCD, DDJ, and RJ jitter

components that is difficult to implement with production test

equipment. The receiver can be equivalently tested to the worst-

case FDDI PMD input jitter conditions and meet the minimum

output data window time-width of 2.13 ns. This is accomplished by

using a nearly ideal input optical signal (no DCD, insignificant DDJ

and RJ) and measuring for a wider window time-width of 4.6 ns.

This is possible due to the cumulative effect of jitter components

through their superposition (DCD and DDJ are directly additive

and RJ components are rms additive). Specifically, when a nearly

ideal input optical test signal is used and the maximum receiver

peak-topeak jitter contributions of DCD (0.4 ns), DDJ (1.0 ns), and

RJ (2.14 ns) exist, the minimum window time-width becomes

8.0 ns – 0.4 ns – 1.0 ns – 2.14 ns = 4.46 ns, or conservatively 4.6 ns.

This wider window time-width of 4.6 ns guarantees the FDDI PMD

Annex E minimum window time-width of 2.13 ns under worst-case

input jitter conditions to the Avago Technologies’ receiver.