9

HCMS-29xx Write Cycle Diagram

NOTE:

1. DATA IS COPIED TO THE CONTROL REGISTER OR THE DOT LATCH AND LED OUTPUTS WHEN CE IS HIGH AND CLK IS LOW.

RSH

T

CES

T

CLKH

T

CLKL

T

CEH

T

DS

T

DH

T

CEDO

T

DOUT

T

DOUTP

T

PREVIOUS DATA

NEW DATA

NEW DATA LATCHED HERE

[1]

CE

RS

CLK

D

IN

LED OUTPUTS,

CONTROL

REGISTERS

(SIMULTANEOUS)

OUT

D

D

(SERIAL)

OUT

2

1

3

4

11

12

6

7

8

10

9

5

Control Word 0

display  brightness  by  pulse  width  modulating  the  LED 

operation or sleep mode.

Internal Display Oscillator and the LED pixel drivers. This 

mode is used when the IC needs to be powered up, but 

does not need to be active. Current draw in sleep mode 

is nearly zero. Data in the Dot Register and Control Words 

are retained during sleep mode.

Control Register

The Control Register allows software modification of the 

IC’s  operation  and  consists  of  two  independent  7-bit 

the  two  7-bit  control  words.  Control  Word  0  performs 

pulse  width  modulation  brightness  control,  peak  pixel 

current brightness control, and sleep mode. Control Word 

1 sets serial/simultaneous data out mode, and external 

oscillator  prescaler.  Each  function  is  independent  of 

the others. 

Control Register Data Loading

Data  is  loaded  into  the  Control  Register,  MSB  first,  ac-

cording  to  the  procedure  shown  in  Table  1  and  the 

Write Cycle Timing Diagram. First, RS is brought to logic 

high  and  then  CE  is  brought  to  logic  low.  Next,  each 

successive rising CLK edge will shift in the data on the 

line  is  brought  to  logic  high.  When  CLK  goes  to  logic 

low, new data is copied into the selected control word. 

Loading data into the Control Register takes place while 

the previous control word configures the display.