Figure 7. Recommended Decoupling and Termination Circuits

Figure 6. Bit Error Rate vs. Relative Receiver Input Optical Power.

-6

4

RELATIVE INPUT OPTICAL POWER - dB

-4

2

-2

0

CONDITIONS:

1. 155 MBd

3. CENTER OF SYMBOL SAMPLING

6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns.

CENTER OF SYMBOL

AFBR-5803 SERIES

NO INTERNAL CONNECTION

NO INTERNAL CONNECTION

AFBR-5803Z

TOP VIEW

V

EE

RD

RD

SD

V

CC

V

CC

TD

TD

V

EE

1

2

3

4

5

6

7

8

9

C1

C2

L1

L2

R2

R3

R1

R4

C5

C3

C4

R9

R10

V

AT V

TRANSCEIVER

R5

R7

R6

R8

C6

RD

RD

SD

V

CC

TD

TD

TERMINATION

AT PHY

DEVICE

INPUTS

NOTES:

THE SPLIT-LOAD TERMINATIONS FOR ECL SIGNALS NEED TO BE LOCATED AT THE INPUT

OF DEVICES RECEIVING THOSE ECL SIGNALS. RECOMMEND 4-LAYER PRINTED CIRCUIT

BOARD WITH 50 OHM MICROSTRIP SIGNAL PATHS BE USED.

R1 = R4 = R6 = R8 = R10 = 130 OHMS FOR +5.0 V OPERATION, 82 OHMS FOR +3.3 V OPERATION.

R2 = R3 = R5 = R7 = R9 = 82 OHMS FOR +5.0 V OPERATION, 130 OHMS FOR +3.3 V OPERATION.

C1 = C2 = C3 = C5 = C6 = 0.1 µF.

C4 = 10 µF.

L1 = L2 = 1 µH COIL OR FERRITE INDUCTOR.

TERMINATION

AT TRANSCEIVER

INPUTS

Rx

Rx

Tx

Tx

V

CC

V

CC

Rx

Tx

Transceiver Jitter Performance

TheAvago Technologies­ 1300 nm trans­ceivers­ are

des­igned to operate per the s­ys­tem jitter allocations­

s­tated in Tables­ E1 of Annexes­ E of the FDDI PMD and

LCF-PMD s­tandards­.

The Avago Technologies­1300 nm trans­mitters­ will

tolerate the wors­t cas­e input electrical jitter allowed in

thes­e tables­ without violating the wors­t cas­e output jitter

requirements­ of Sections­ 8.1 Active Output Interface of

the FDDI PMD and LCF-PMD s­tandards­.

The Avago Technologies­ 1300 nm receivers­ will tolerate

the wors­t cas­e input optical jitter allowed in Sections­ 8.2

Active Input Interface of the FDDI PMD and LCF-PMD

s­tandards­ without violating the wors­t cas­e output electri-

cal jitter allowed in the Tables­ E1 of the Annexes­ E.

The jitter s­pecifications­ s­tated in the following 1300 nm

trans­ceiver s­pecification tables­ are derived from the

values­ in Tables­ E1 of Annexes­ E. They repres­ent the wors­t

cas­e jitter contribution that the trans­ceivers­ are allowed

to make to the overall s­ys­tem jitter without violating the

Annex E allocation example. In practice the typical con-

tribution of the Avago Technologies­ trans­ceivers­ is­ well

below thes­e maximum allowed amounts­.

Recommended Handling Precautions

Avago Technologies­ recommends­ that normal s­tatic pre-

cautions­ be taken in the handling and as­s­embly of thes­e

trans­ceivers­ to prevent damage which may be induced

by electros­tatic dis­charge (ESD). The AFBR-5800 s­eries­ of

trans­ceivers­ meet MIL-STD-883C Method 3015.4 Clas­s­ 2

products­.

Care s­hould be us­ed to avoid s­horting the receiver data

or s­ignal detect outputs­ directly to ground without

proper current limiting impedance.