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B300W35A102XYG Datasheet(PDF) 2 Page - ON Semiconductor |
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B300W35A102XYG Datasheet(HTML) 2 Page - ON Semiconductor |
2 / 31 page BelaSigna 300 http://onsemi.com 2 • Integrated A/D Converters and Powered Output: minimize need for external components • Flexible Clocking Architecture: supports speeds up to 40 MHz • “Smart” Power Management: including low current standby mode requiring only 0.06 mA • Diverse Memory Architecture: 4864x48−bit words of shared memory between the CFX core and the HEAR accelerator plus 8−Kword DSP core data memory, 12−Kwords of 32−bit DSP core program memory as well as other memory banks • Data Security: sensitive program data can be encrypted for storage in external NVRAM to prevent unauthorized parties from gaining access to proprietary software intellectual property, 128−bit AES encryption • Development Tools: interface hardware with USB support as well as a full IDE that can be used for every step of program development including testing and debugging • These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Contents Introduction 1 .................................................................................... Figures and Data 3 ................................................................................. Mechanical Information and Circuit Design Guidelines 6 .................................................. Architecture Overview 12 ........................................................................... Application Diagrams 25 ........................................................................... Assembly Information 27 ........................................................................... Miscellaneous 29 .................................................................................. |
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