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CAT34TS02VP2GT4B Datasheet(PDF) 3 Page - ON Semiconductor |
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CAT34TS02VP2GT4B Datasheet(HTML) 3 Page - ON Semiconductor |
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3 / 20 page  CAT34TS02 http://onsemi.com 3 Table 5. A.C. CHARACTERISTICS (VCC = 3.3 V ± 10%, TA = −20°C to +125°C) (Note 4) Symbol Parameter Min Max Units FSCL (Note 5) Clock Frequency 10 400 kHz tHIGH High Period of SCL Clock 600 ns tLOW Low Period of SCL Clock 1300 ns tTIMEOUT (Note 5) SMBus SCL Clock Low Timeout 25 35 ms tR (Note 6) SDA and SCL Rise Time 300 ns tF (Note 6) SDA and SCL Fall Time 300 ns tSU:DAT (Note 7) Data Setup Time 100 ns tSU:STA START Condition Setup Time 600 ns tHD:STA START Condition Hold Time 600 ns tSU:STO STOP Condition Setup Time 600 ns tBUF Bus Free Time Between STOP and START 1300 ns tHD:DAT Input Data Hold Time 0 ns tDH (Note 6) Output Data Hold Time 200 900 ns Ti Noise Pulse Filtered at SCL and SDA Inputs 100 ns tWR Write Cycle Time 5 ms tPU (Note 8) Power−up Delay to Valid Temperature Recording 100 ms 4. Timing reference points are set at 30%, respectively 70% of VCC, as illustrated in Figure 23. Bus loading must be such as to allow meeting the VIL, VOL as well as the various timing limits. 5. For the CAT34TS02 Rev. B, the TS interface will reset itself and will release the SDA line if the SCL line stays low beyond the tTIMEOUT limit. The time−out count is started (and then re−started) on every negative transition of SCL in the time interval between START and STOP. The minimum clock frequency of 10 kHz is an SMBus recommendation; the minimum operating clock frequency for the CAT34TS02’s SPD component is DC, while the minimum operating frequency for the TS component is limited only by the SMBus time−out. For the CAT34TS02 Rev. C, both the TS and the SPD implement the time−out feature. 6. In a “Wired−OR” system (such as I2C or SMBus), SDA rise time is determined by bus loading. Since each bus pull−down device must be able to sink the (external) bus pull−up current (in order to meet the VIL and/or VOL limits), it follows that SDA fall time is inherently faster than SDA rise time. SDA rise time can exceed the standard recommended tR limit, as long as it does not exceed tLOW − tDH − tSU:DAT, where tLOW and tDH are actual values (rather than spec limits). A shorter tDH leaves more room for a longer SDA tR, allowing for a more capacitive bus or a larger bus pull−up resistor. At the minimum tLOW spec limit of 1300 ns, the maximum tDHof 900 ns demands a maximum SDA tR of 300 ns. The CAT34TS02’s maximum tDH is <700 ns, thus allowing for an SDA tR of up to 500 ns at minimum tLOW. 7. The minimum tSU:DAT of 100 ns is a limit recommended by standards. The CAT34TS02 will accept a tSU:DAT of 0 ns. 8. The first valid temperature recording can be expected after tPU at nominal supply voltage. Table 6. PIN CAPACITANCE (TA = 25°C, VCC = 3.3 V, f = 1 MHz) Symbol Parameter Test Conditions/Comments Min Max Unit CIN SDA, EVENT Pin Capacitance VIN = 0 8 pF Input Capacitance (other pins) VIN = 0 6 pF |
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