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CAT93C66VI-GT3 Datasheet(PDF) 5 Page - ON Semiconductor |
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CAT93C66VI-GT3 Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 16 page CAT93C66, CAT93W66 http://onsemi.com 5 Device Operation The CAT93C66 is a 4096−bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93C66 can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 11−bit instructions control the reading, writing and erase operations of the device. When organized as X8, seven 12−bit instructions control the reading, writing and erase operations of the device. The CAT93W66 works in x16 mode only. The device operates on a single power supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The serial communication protocol follows the timing shown in Figure 2. The ready/busy status can be determined after the start of internal write cycle by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy “1” into the DI pin. The DO pin will enter the high impedance state on the rising edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The format for all instructions sent to the device is a logical “1” start bit, a 2−bit (or 4−bit) opcode, 8−bit address (an additional bit when organized X8) and for write operations a 16−bit data field (8−bit for X8 organizations). The instruction format is shown in Instruction Set table. Table 11. INSTRUCTION SET Instruction Start Bit Opcode Address Data Comments x8 (Note 11) x16 x8 (Note 11) x16 READ 1 10 A8−A0 A7−A0 Read Address AN – A0 ERASE 1 11 A8−A0 A7−A0 Clear Address AN – A0 WRITE 1 01 A8−A0 A7−A0 D7−D0 D15−D0 Write Address AN – A0 EWEN 1 00 11XXXXXXX 11XXXXXX Write Enable EWDS 1 00 00XXXXXXX 00XXXXXX Write Disable ERAL 1 00 10XXXXXXX 10XXXXXX Clear All Addresses WRAL 1 00 01XXXXXXX 01XXXXXX D7−D0 D15−D0 Write All Addresses 11. The x8 memory organization is available for the CAT93C66 only. |
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