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MAX6324HUT29 Datasheet(PDF) 6 Page - Maxim Integrated Products |
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MAX6324HUT29 Datasheet(HTML) 6 Page - Maxim Integrated Products |
6 / 13 page µP Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset 6 _______________________________________________________________________________________ Detailed Description The MAX6323/MAX6324 µP supervisory circuits main- tain system integrity by alerting the µP to fault condi- tions. In addition to a standard VCC monitor (for power-on reset, brownout detect, and power-down reset), the devices include a sophisticated watchdog timer that detects when the processor is running out- side an expected window of operation for a specific application. The watchdog signals a fault when the input pulses arrive too early (faster than the selected tWD1 timeout period) or too late (slower than the select- ed tWD2 timeout period) (Figure 1). Incorrect timing can lead to poor or dangerous system performance in tight- ly controlled operating environments. Incorrect timing could be the result of improper µP clocking or code execution errors. If a timing error occurs, the MAX6323/MAX6324 issue a watchdog pulse output, independent from the reset output, indicating that sys- tem maintenance may be required. Watchdog Function A pulse on the watchdog output WDPO can be trig- gered by a fast fault or a slow fault. If the watchdog input (WDI) has two falling edges too close to each other (faster than tWD1) (Figure 2) or falling edges that are too far apart (slower than tWD2) (Figure 3), WDPO is pulsed low. Normal watchdog operation is displayed in Figure 4 (WDPO is not asserted). The internal watch- dog timer is cleared when a WDI falling edge is detect- ed within the valid watchdog window or when the device’s RESET or WDPO outputs are deasserted. All WDI input pulses are ignored while either RESET or WDPO is asserted. Figure 1 identifies the input timing regions where WDPO fault outputs will be observed with respect to tWD1 and tWD2. After RESET or WDPO deasserts, the first WDI falling edge is ignored for the fast fault condition (Figure 2). Upon detecting a watchdog fault, the WDPO output will pulse low for 1ms. WDPO is an open-drain output. Connect a pullup resistor on WDPO to any supply up to +6V. VCC Reset The MAX6323/MAX6324 also include a standard VCC reset monitor to ensure that the µP is started in a known state and to prevent code execution errors during power-up, power-down, or brownout conditions. RESET is asserted whenever the VCC supply voltage *UNDETERMINED STATES MAY OR MAY NOT GENERATE A FAULT CONDITION. POSSIBLE STATES GUARANTEED TO ASSERT WDPO GUARANTEED TO ASSERT WDPO GUARANTEED NOT TO ASSERT WDPO FAST FAULT CONDITION 1 SLOW FAULT CONDITION 3 NORMAL OPERATION CONDITION 2 tWD1 (min) ) tWD1 (max) tWD2 (min) tWD2 (max) *UNDETERMINED *UNDETERMINED Figure 1. Detailed Watchdog Input Timing Relationship |
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