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Functional Description

Enhanced Configuration (EPC) Devices Datasheet

January 2012

Altera Corporation

Fast Passive Parallel Configuration

Stratix series and APEX II devices can be configured using the EPC device in the FPP

configuration mode. In this mode, the EPC device sends a byte of data on the

DATA[7..0]

pins, which connect to the DATA[7..0] input pins of the FPGA, per DCLK

cycle. Stratix series and APEX II FPGAs receive byte-wide configuration data per DCLK

cycle. Figure 2 shows the EPC device in FPP configuration mode. In this figure, the

external flash interface is not used and hence most flash pins are left unconnected

(with the few noted exceptions).

resistor values, supply voltages, and MSEL pin settings, refer to the configuration

chapter in the appropriate device handbook.

Figure 2. FPP Configuration

Notes to Figure 2:

(2) The nINIT_CONF pin is available on EPC devices and has an internal pull-up resistor that is always active. This means an external pull-up

resistor is not required on the nINIT_CONF or nCONFIG signal. The nINIT_CONF pin does not need to be connected if its functionality is not

(3) The EPC devices’ OE and nCS pins have internal programmable pull-up resistors. If internal pull-up resistors are used, external pull-up resistors

resistors, check the Disable nCS and OE pull-ups on configuration device option when generating programming files.

(4) For PORSEL, PGM[], and EXCLK pin connections, refer to Table 10 on page 24.

(5) In the 100-pin PQFP package, you must externally connect the following pins: C-A0 to F-A0, C-A1 to F-A1, C-A15 to F-A15, C-A16 to

F-A16

(6) Connect the FPGA MSEL[] input pins to select the FPP configuration mode. For more information, refer to the configuration chapter in the

appropriate device handbook.

Protection” on page 16.

EPC Device

DCLK

DATA[7..0]

OE

nCS

nINIT_CONF (2)

MSEL

DCLK

DATA[7..0]

nSTATUS

CONF_DONE

nCONFIG

GND

GND

(3)

(3)

nCE

EXCLK

Stratix Series

or

APEX II Device

WE#C

RP#C

WP#

PORSEL

PGM[2..0]

TMO

WE#F

RP#F

A[20..0]

RY/BY#

CE#

OE#

DQ[15..0]

N.C.

N.C.

N.C.

N.C.

N.C.

BYTE# (5)

TM1

(3)

(3)

C-A0 (5)

C-A1 (5)

C-A15 (5)

C-A16 (5)

A0-F

A1-F

A15-F

A16-F

(1)

(1)

n

(6)

(1)

nCEO

N.C.

(4)

(4)

(4)

VCCW