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HEF4014BT653 Datasheet(PDF) 4 Page - NXP Semiconductors |
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HEF4014BT653 Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 14 page HEF4014B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 8 — 21 November 2011 4 of 14 NXP Semiconductors HEF4014B 8-bit static shift register 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; nD = HIGH or LOW; = LOW-to-HIGH clock transition; = HIGH-to-LOW clock transition; 8. Limiting values [1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C. [2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C. Table 3. Function table[1] Number of clock transitions Inputs Outputs CP DS PE Q5 Q6 Q7 Serial operation 1 1D L XXX 2 2D L XXX 3 3D L XXX 6 XL 1D X X 7 XL 2D 1D X 8 X L 3D 2D 1D X X no change no change no change Parallel operation 1 X H D5 D6 D7 X X no change no change no change Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDD supply voltage 0.5 +18 V IIK input clamping current VI < 0.5 V or VI >VDD + 0.5 V - 10 mA VI input voltage 0.5 VDD + 0.5 V IOK output clamping current VO < 0.5 V or VO >VDD + 0.5 V - 10 mA II/O input/output current - 10 mA IDD supply current - 50 mA Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +85 C Ptot total power dissipation Tamb = 40 C to +85 C DIP16 package [1] - 750 mW SO16 package [2] - 500 mW P power dissipation per output - 100 mW |
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