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ML4841 Datasheet(PDF) 9 Page - Fairchild Semiconductor

Part # ML4841
Description  Variable Feedforward PFC/PWM Controller Combo
Download  15 Pages
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

ML4841 Datasheet(HTML) 9 Page - Fairchild Semiconductor

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PRODUCT SPECIFICATION
ML4841
REV. 1.0.3 6/13/01
9
There are two major concerns when compensating the
voltage loop error amplifier; stability and transient response.
Optimizing interaction between transient response and
stability requires that the error amplifier’s open-loop cross-
over frequency should be 1/2 that of the line frequency, or
23Hz for a 47Hz line (lowest anticipated international power
frequency). The gain vs. input voltage of the ML4841’s
voltage error amplifier has a specially shaped nonlinearity
such that under steady-state operating conditions the
transconductance of the error amplifier is at a local
minimum. Rapid perturbations in line or load conditions
will cause the input to the voltage error amplifier (VFB) to
deviate from its 2.5V (nominal) value. If this happens, the
transconductance of the voltage error amplifier will increase
significantly, as shown in the Typical Performance Charac-
teristics. This increases the gain-bandwidth product of the
voltage loop, resulting in a much more rapid voltage loop
response to such perturbations than would occur with a
conventional linear gain characteristic.
The current amplifier compensation is similar to that of the
voltage error amplifier with the exception of the choice of
crossover frequency. The crossover frequency of the current
amplifier should be at least 10 times that of the voltage
amplifier, to prevent interaction with the voltage loop. It
should also be limited to less than 1/6th that of the switching
frequency, e.g. 16.7kHz for a 100kHz switching frequency.
For more information on compensating the current and volt-
age control loops, see Application Notes 33 and 34. Appli-
cation Note 16 also contains valuable information for the
design of this class of PFC.
Oscillator (RT/CT)
The oscillator frequency is determined by the values Of RT
and CT, which determine the ramp and off-time of the
oscillator output clock:
The ramp-charge time of the oscillator is derived from the
following equation:
at VREF = 7.5V:
The discharge time of the oscillator may be determined
using:
The deadtime is so small (tRAMP >> tDEADTIME) that the
operating frequency can typically be approximated by:
EXAMPLE:
For the application circuit shown in the data sheet, with the
oscillator running at:
Solving for RT x CT yields 1 x 10
-5. Selecting standard com-
ponents values, CT = 390pF, and RT = 24.9k
Ω.
RAMP 1
The ramp voltage on this pin serves as a reference to which
the PFC’s current error amp output is compared in order to
set the duty cycle of the PFC switch. The external ramp volt-
age is derived from a RC network similar to the oscillator’s.
The PWM’s oscillator sends a synchronous pulse every other
cycle to reset this ramp.
The ramp voltage should be limited to no more than the out-
put high voltage (6V) of the current error amplifier. The tim-
ing resistor value should be selected such that the capacitor
will not charge past this point before being reset. In order to
ensure the linearity of the PFC loop’s transfer function and
improve noise immunity, the charging resistor should be
connected to the 13.5V VCC rather than the 7.5V reference.
This will keep the charging voltage across the timing cap in
the "linear" region of the charging curve.
The component value selection is similar to oscillator RC
component selection.
The charge time of Ramp 1 is derived from the following
equations:
At VCC = 13.5V and assuming Ramp Peak = 5V to allow for
component tolerances:
The capacitor value should remain small to keep the dis-
charge energy and the resulting discharge current through the
part small. A good value to use is the same value used in the
PWM timing circuit (CT).
For the application circuit shown in the data sheet, using a
200kHz PWM and 390pF timing cap yields RT:
f
OSC
1
t
RAMP
t
DISCHARGE
+
-------------------------------------------------------
=
(2)
t
RAMP
C
T
R
T
×
In
V
REF
1.25
V
REF
3.75
--------------------------------


×
=
(3)
t
RAMP
C
T
R
T
×
0.51
×
=
t
DISCHARGE
2.5V
5.1mA
------------------
C
T
×
490
C
T
×
==
(4)
f
OSC
1
t
RAMP
----------------
=
(5)
t
RAMP
0.51
R
T
×
C
T
×
510
6
×
==
f
OSC
200kHz
1
t
RAMP
----------------
==
f
OSC
1
t
CHARGE
t
DISCHARGE
+
--------------------------------------------------------------
=
(6)
t
CHARGE
2
f
OSC
------------
=
(7)
t
CHARGE
C
T
R
T
×
In
V
CC
Ramp Valley
V
CC
Ramp Peak
---------------------------------------------------


×
=
(8)
t
CHARGE
0.463
R
T
×
C
T
×
=
(9)
R
T
110
5
×
0.463
() 390 10
12
×
()
--------------------------------------------------------
56.2k
==
(10)


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