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ML6426CS-3 Datasheet(PDF) 2 Page - Fairchild Semiconductor |
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ML6426CS-3 Datasheet(HTML) 2 Page - Fairchild Semiconductor |
2 / 17 page ML6426 DATA SHEET 2 REV. 3A August 2004 Pin Configuration Pin Description PIN NAME FUNCTION 1 A/B MUX Logic input pin to select between Bank <A> and Bank <B> video inputs. This pin is internally pulled high. 2RINA/YINA Unfiltered analog R- or Y-channel input for Bank <A>. Sync must be provided at SYNC IN pin. 3 GND Analog ground 4VCC Analog 5V supply 5RINB/YINB Unfiltered analog R- or Y-channel input for Bank <B>. Sync must be provided at SYNC IN pin. 6GINA/UINA Unfiltered analog G- or U-channel input for Bank <A>. Sync must be provided at SYNC IN pin. 7GINB/UINB Unfiltered analog G- or U-channel input for Bank <B>. Sync must be provided at SYNC IN pin. 8BINA/VINA Unfiltered analog B- or V-channel input for Bank <A>. Sync must be provided at SYNC IN pin. 9BINB/VINB Unfiltered analog B- or V-channel input for Bank <B>. Sync must be provided at SYNC IN pin. 10 BOUT Analog B or V-channel output 11 GOUT Analog G or U-channel output 12 VCCO 5V power supply for output buffers 13 ROUT Analog R or Y-channel output 14 GNDO Analog ground 15 DISABLE Disable/Enable pin. Turns the chip off when logic high. Internally pulled low. 16 SYNC IN Input for an external H-sync logic signal for filter channels. CMOS level input. Active High. ML6426 16-Pin Narrow SOIC (S16N) 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 TOP VIEW A/B MUX RINA/YINA GND VCC RINB/YINB GINA/UINA GINB/UINB BINA/VINA SYNC IN DISABLE GNDO ROUT/YOUT VCCO GOUT/UOUT BOUT/VOUT BINB/VINB |
Similar Part No. - ML6426CS-3 |
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Similar Description - ML6426CS-3 |
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