C8051F920-F-GM datasheet(11/330 Pages) SILABS

Part #	C8051F920-F-GM

Description	Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

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Manufacturer	SILABS [Silicon Laboratories]

Direct Link	http://www.silabs.com

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11 / 330 page

Rev. 1.3

11

C8051F93x-C8051F92x

Figure 24.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram

271

Figure 24.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram

271

Figure 24.5. Master Mode Data/Clock Timing ........................................................ 273

Figure 24.6. Slave Mode Data/Clock Timing (CKPHA = 0) .................................... 274

Figure 24.7. Slave Mode Data/Clock Timing (CKPHA = 1) .................................... 274

Figure 24.8. SPI Master Timing (CKPHA = 0)........................................................ 280

Figure 24.9. SPI Master Timing (CKPHA = 1)........................................................ 280

Figure 24.10. SPI Slave Timing (CKPHA = 0)........................................................ 281

Figure 24.11. SPI Slave Timing (CKPHA = 1)........................................................ 281

Figure 25.1. T0 Mode 0 Block Diagram.................................................................. 286

Figure 25.2. T0 Mode 2 Block Diagram.................................................................. 287

Figure 25.3. T0 Mode 3 Block Diagram.................................................................. 288

Figure 25.4. Timer 2 16-Bit Mode Block Diagram .................................................. 293

Figure 25.5. Timer 2 8-Bit Mode Block Diagram .................................................... 294

Figure 25.6. Timer 2 Capture Mode Block Diagram ............................................... 295

Figure 25.7. Timer 3 16-Bit Mode Block Diagram .................................................. 299

Figure 25.8. Timer 3 8-Bit Mode Block Diagram. ................................................... 300

Figure 25.9. Timer 3 Capture Mode Block Diagram ............................................... 301

Figure 26.1. PCA Block Diagram............................................................................ 305

Figure 26.2. PCA Counter/Timer Block Diagram.................................................... 306

Figure 26.3. PCA Interrupt Block Diagram ............................................................. 307

Figure 26.4. PCA Capture Mode Diagram.............................................................. 309

Figure 26.5. PCA Software Timer Mode Diagram .................................................. 310

Figure 26.6. PCA High-Speed Output Mode Diagram............................................ 311

Figure 26.7. PCA Frequency Output Mode ............................................................ 312

Figure 26.8. PCA 8-Bit PWM Mode Diagram ......................................................... 313

Figure 26.9. PCA 9, 10 and 11-Bit PWM Mode Diagram ....................................... 314

Figure 26.10. PCA 16-Bit PWM Mode.................................................................... 315

Figure 26.11. PCA Module 5 with Watchdog Timer Enabled ................................. 316

Figure 27.1. Typical C2 Pin Sharing....................................................................... 327

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C8051F920-F-GM Datasheet(PDF) 11 Page - Silicon Laboratories

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