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ACPL-054L-560E Datasheet(PDF) 10 Page - AVAGO TECHNOLOGIES LIMITED |
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ACPL-054L-560E Datasheet(HTML) 10 Page - AVAGO TECHNOLOGIES LIMITED |
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10 / 16 page  10 Switching Specifications (ACPL-054L/W50L/K54L) Over recommended operating (TA = -40°C to 105°C), IF = 3mA, (2.7V ≤ VCC ≤ 24V), unless otherwise specified. Parameter Symbol Min Typ Max Units Test Conditions Fig. Propagation Delay Time to Logic Low at Output TPHL 0.2 0.5 s TA=25°C Pulse: f=10kHz, Duty cycle=50%, IF=3mA, VCC=3.3 V, RL= 1.8k , CL=15pF, VTHHL=1.5V 14 0.2 1 s 6b, 14 0.22 0.5 s TA=25°C Pulse: f=10kHz, Duty cycle=50%, IF=3mA, VCC=5.0 V, RL= 2.9k , CL=15pF, VTHHL=1.5V 14 0.22 1 s 7b, 14 0.33 0.7 s TA=25°C Pulse: f=10kHz, Duty cycle=50%, IF=3mA, VCC=24V, RL=14.8k , CL=15pF, VTHHL=1.5V 14 0.33 1.3 s 8b, 14 Propagation Delay Time to Logic High at Output TPLH 0.38 0.8 s TA=25°C Pulse: f=10kHz, Duty cycle=50%, IF=3mA, VCC=3.3 V, RL=1.8k , CL=15pF, VTHHL=2.0V 14 0.38 1.4 s 6b, 14 0.31 0.7 s TA=25°C Pulse: f=10kHz, Duty cycle=50%, IF=3mA, VCC=5.0 V, RL=2.9k , CL=15pF, VTHHL=2.0V 14 0.31 1 s 7b, 14 0.3 0.7 s TA=25°C Pulse: f=10kHz, Duty cycle=50%, IF=3mA, VCC=24V, RL=14.8k , CL=15pF, VTHHL=2.0V 14 0.3 1 s 8b, 14 Pulse Width Distortion[1] PWD 0.18 0.8 s TA=25°C Pulse: f=10kHz, Duty cycle=50%, IF=3mA, VCC=3.3 V, RL=1.8k , CL=15pF, VTHHL=1.5V, VTHLH=2.0V 14 0.18 1.4 s 14 0.1 0.7 s TA=25°C Pulse: f=10kHz, Duty cycle=50%, IF=3mA, VCC=5.0V, RL = 2.9k , CL=15pF, VTHHL=1.5V, VTHLH=2.0V 14 0.1 1 s 14 0.1 0.7 s TA=25°C Pulse: f=10kHz, Duty cycle=50%, IF=3mA, VCC=24V, RL=14.8k , CL=15pF, VTHHL=1.5V, VTHLH=2.0V 14 0.1 1 s 14 Propagation Delay Difference Between Any two Parts[2] tpsk 0.18 0.7 s TA=25°C Pulse: f=10kHz, Duty cycle=50%, IF=3mA, VCC=3.3 V, RL=1.8k , CL=15pF, VTHHL=1.5V, VTHLH=2.0V 0.1 0.6 s TA=25°C Pulse: f=10kHz, Duty cycle=50%, IF=3mA, VCC=5.0V, RL=2.9k , CL=15pF, VTHHL=1.5V, VTHLH=2.0V 0.1 0.6 s TA=25°C Pulse: f=10kHz, Duty cycle=50%, IF=3mA, VCC=24V, RL=14.8k , CL=15pF, VTHHL=1.5V, VTHLH=2.0V Common Mode Transient Immunity at Logic High Output[3] |CMH| 1525 kV/ s VCM=1500V, IF=0mA, TA=25°C, RL=1.8k or 2.9k, VCC=3.3 V or 5V 15 Common Mode Transient Immunity at Logic Low Output[4] |CML| 1520 kV/ s VCM=1500V, IF=4mA, TA=25°C, RL=2.9k , VCC=5V 15 15 20 kV/ s VCM=1500V, IF=3mA, TA=25°C, RL=1.8k , VCC=3.3 V 15 Notes: 1. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given device. 2. The difference between tPLH and tPHL between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay Specifications section.) 3. Common transient immunity in a Logic High level is the maximum tolerable (positive) dVCM/dt on the rising edge of the common mode pulse, VCM, to assure that the output will remain in a Logic High state (i.e., VO > 2.0 V). 4. Common mode transient immunity in a Logic Low level is the maximum tolerable (negative) dVCM/dt on the falling edge of the common mode pulse signal, VCM to assure that the output will remain in a Logic Low state (i.e., VO < 0.8 V). |
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