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ACSL-6310-00TE Datasheet(PDF) 10 Page - AVAGO TECHNOLOGIES LIMITED

Part # ACSL-6310-00TE
Description  Multi-Channel and Bi-Directional, 15 MBd Digital Logic Gate Optocoupler
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Manufacturer  AVAGO [AVAGO TECHNOLOGIES LIMITED]
Direct Link  http://www.avagotech.com
Logo AVAGO - AVAGO TECHNOLOGIES LIMITED

ACSL-6310-00TE Datasheet(HTML) 10 Page - AVAGO TECHNOLOGIES LIMITED

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10
Electrical Specifications
Over recommended operating range (3.0V ≤ V
DD1
≤ 3.6V, 3.0V ≤ V
DD2
≤ 3.6V, T
A
= -40°C to +100°C) unless otherwise specified.
All typical specifications are at T
A
= +25°C , V
DD1
= V
DD2
= +3.3V.
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Input Threshold Current
I
TH
2.7
7.0
mA
I
OL(Sinking)
=13 mA, V
O
= 0.6V
High Level Output Current
I
OH
4.7
100.0
μA
I
F
= 250 μA, V
O
= 3.3V
Low Level Output Voltage
V
OL
0.36
0.68
V
I
OL(Sinking)
= 13 mA, I
F
= 7mA
High Level Supply Current
I
DDH
3.2
5.0
mA
I
F
= 0 mA
(per channel)
Low Level Supply Current
I
DDL
4.6
7.5
mA
I
F
= 10 mA
(per channel)
Input Forward Voltage
V
F
1.25
1.52
1.80
V
I
F
= 10 mA, T
A
= 25°C
Input Reverse Breakdown Voltage
BV
R
5.0
V
I
R
= 10 μA
Input Diode Temperature Coefficient
∆V
F
/ ∆T
A
-1.8
mV/°C
I
F
= 10 mA
Input Capacitance
C
IN
80
pF
f = 1 MHz, V
F
= 0V
Switching Specifications
Over recommended operating range (3.0V ≤ V
DD1
≤ 3.6V, 3.0V ≤ V
DD2
≤ 3.6V, I
F
= 8.0 mA, T
A
= -40°C to +100°C) unless otherwise
specified. All typical specifications are at T
A
= +25°C , V
DD1
= V
DD2
= +3.3V.
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Maximum Data Rate
10
15
MBd
R
L
= 350Ω, C
L
= 15 pF
Pulse Width
t
PW
100
ns
R
L
= 350Ω, C
L
= 15 pF
Propagation Delay Time
t
PLH
52
100
ns
R
L
= 350Ω, C
L
= 15 pF
to Logic High Output Level[5]
Propagation Delay Time
t
PHL
44
100
ns
R
L
= 350Ω, C
L
= 15 pF
to Logic Low Output Level [6]
Pulse Width Distortion |t
PHL
– t
PLH
|
|PWD|
8
35
ns
R
L
= 350Ω, C
L
= 15 pF
Propagation Delay Skew[7]
t
PSK
40
ns
R
L
= 350Ω, C
L
= 15 pF
Output Rise Time (10 – 90%)
t
R
35
ns
R
L
= 350Ω, C
L
= 15 pF
Output Fall Time (10 – 90%)
t
F
12
ns
R
L
= 350Ω, C
L
= 15 pF
Logic High Common Mode
|CM
H
|
10
kV/μs
V
cm
= 1000V, I
F
= 0 mA,
Transient Immunity [8]
V
O
= 2.0V, R
L
= 350Ω,
T
A
= 25°C
Logic Low Common Mode
|CM
L
|
10
kV/μs
V
cm
= 1000V, I
F
= 8 mA,
Transient Immunity [8]
V
O
= 0.8V, R
L
= 350Ω,
T
A
= 25°C
Notes:
5. t
PLH
is measured from the 4.0 mA level on the falling edge of the input pulse to the 1.5V level on the rising edge of the output pulse.
6. t
PHL
is measured from the 4.0 mA level on the rising edge of the input pulse to the 1.5V level on the falling edge of the output pulse.
7. t
PSK
is equal to the worst case difference in t
PHL
and/or t
PLH
that will be seen between units at any given temperature and specified test condi-
tions.
8. CM
H
is the maximum common mode voltage slew rate that can be sustained while maintaining V
O
> 2.0V. CM
L
is the maximum common mode
voltage slew rate that can be sustained while maintaining V
O
< 0.8V. The common mode voltage slew rates apply to both rising and falling
common mode voltage edges.


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