4

ATtiny25/45/85 [DATASHEET]

2586PS–AVR–06/2013

2.

Overview

The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By

executing powerful instructions in a single clock cycle, the ATtiny25/45/85 achieves throughputs approaching 1

MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

2.1

Block Diagram

Figure 2-1.

Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are

directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one

single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving

throughputs up to ten times faster than conventional CISC microcontrollers.

PROGRAM

COUNTER

CALIBRATED

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

STACK

POINTER

PROGRAM

FLASH

SRAM

MCU CONTROL

REGISTER

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

REGISTER

TIMER/

COUNTER0

SERIAL

UNIVERSAL

INTERFACE

TIMER/

COUNTER1

INSTRUCTION

DECODER

DATA DIR.

REG.PORT B

DATA REGISTER

PORT B

PROGRAMMING

LOGIC

TIMING AND

CONTROL

MCU STATUS

REGISTER

STATUS

REGISTER

ALU

PORT B DRIVERS

PB[0:5]

VCC

GND

CONTROL

LINES

8-BIT DATABUS

Z

ADC /

ANALOG COMPARATOR

INTERRUPT

UNIT

DATA

EEPROM

OSCILLATORS

Y

X

RESET