www.ti.com

HIGH-SPEED CURRENT MODULATOR

MODULATION CURRENT GENERATOR

2-WIRE SERIAL INTERFACE AND CONTROL LOGIC

ONET4291VA

SLLS674 – SEPTEMBER 2005

The data signal is applied to the high-speed current modulator by means of the input signal pins DIN+/DIN–,

which provide on-chip differential 100-

Ω line-termination. The succeeding limiting gain stage ensures sufficient

drive amplitude and edge-speed for driving the current modulator differential pair.

The modulation current is sunk from the common emitter node of the differential pair by means of a modulation

current generator, which is digitally controlled by the 2-wire interface and control logic block.

The collector nodes of the differential pair are connected to the output pins DOUT+/DOUT–, which include

on-chip 2

× 60-Ω back-termination to VCC. The 60-Ω back-termination helps to sufficiently suppress signal

distortion caused by double reflections for VCSEL diodes with impedances ranging from 50

Ω through 75 Ω.

The modulation current generator provides the current for the current modulator described above. The circuit is

digitally controlled by the 2-wire interface and control logic block.

An 8-bit wide control bus, MODC, is used to set the desired modulation current.

Furthermore, two modulation current ranges are selected by means of the MODR signal.

The ENA signal enables or disables the modulation current generator.

The modulation current can be disabled by setting the DIS input pin to a high level. The modulation current is

also disabled in a fault condition if the fault detection enable register flag FLTEN is set.

For more information about the register functionality, see the register mapping description.

The ONET4291VA uses a 2-wire serial interface for digital control. A simplified block diagram of this interface is

shown in Figure 2.

The two circuit inputs, SDA and SCK, are driven, respectively, by the serial data and serial clock from a

microprocessor, for example. Both inputs include 100-k

Ω pullup resistors to VCC. For driving these inputs, an

open drain output is recommended.

A write cycle consists of a START command, three address bits with MSB first, eight data bits with MSB first,

and a STOP command. In idle mode, both SDA and SCK lines are at a high level.

A START command is initiated by the falling edge of SDA with SCK at a high level, transitioning to a low level.

Bits are clocked into an 11-bit wide shift register during the high level of the system clock SCK.

A STOP command is detected on the rising edge of SDA after SCK has changed from a low to a high level.

At the time of detection of a STOP command, the eight data bits from the shift register are copied to a selected

8-bit register. Register selection occurs according to the three address bits in the shift register, which are

decoded to eight independent select signals using a 3 to 8 decoder block.

In the ONET4291VA, only addresses 0 (000b) through 3 (011b) are used.

3