3

7799ES–AVR–09/2012

ATmega8U2/16U2/32U2

2.

Overview

The ATmega8U2/16U2/32U2 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture.

By executing powerful instructions in a single clock cycle, the ATmega8U2/16U2/32U2 achieves throughputs approaching

1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

2.1

Block Diagram

Figure 2-1.

Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

PROGRAM

COUNTER

STACK

POINTER

PROGRAM

FLASH

MCU CONTROL

REGISTER

SRAM

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

REGISTER

TIMER/

COUNTERS

INSTRUCTION

DECODER

DATA DIR.

REG. PORTC

DATA REGISTER

PORTC

INTERRUPT

UNIT

EEPROM

USART1

STATUS

REGISTER

Z

Y

X

ALU

PORTC DRIVERS

PORTD DRIVERS

PORTB DRIVERS

PC7 - PC0

PD7 - PD0

VCC

GND

CONTROL

LINES

PB7 - PB0

D+/SCK

D-/SDATA

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

8-BIT DA TA BUS

USB

PS/2

TIMING AND

CONTROL

OSCILLATOR

CALIB. OSC

DATA DIR.

REG. PORTB

DATA REGISTER

PORTB

ON-CHIP DEBUG

Debug-Wire

PROGRAMMING

LOGIC

DATA DIR.

REG. PORTD

DATA REGISTER

PORTD

POR - BOD

RESET

PLL

SPI

ON-CHIP

3.3V

REGULATOR

UVcc

UCap

1uF