AD9600BCPZ-125 datasheet(4/72 Pages) AD

Part #	AD9600BCPZ-125

Description	10-Bit, 105 MSPS/125 MSPS/150 MSPS

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Manufacturer	AD [Analog Devices]

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AD9600

Rev. B | Page 4 of 72

GENERAL DESCRIPTION

The AD9600 is a dual, 10-bit, 105 MSPS/125 MSPS/150 MSPS

ADC. It is designed to support communications applications

where low cost, small size, and versatility are desired.

The dual ADC core features a multistage, differential pipelined

architecture with integrated output error correction logic. Each

ADC features wide bandwidth, differential sample-and-hold

analog input amplifiers supporting a variety of user-selectable

input ranges. An integrated voltage reference eases design

considerations. A duty cycle stabilizer is provided to compen-

sate for variations in the ADC clock duty cycle, allowing the

converters to maintain excellent performance.

The AD9600 has several functions that simplify the automated

gain control (AGC) function in a communications receiver. For

example, the fast detect feature allows fast overrange detection

by outputting four bits of input level information with very

short latency.

In addition, the programmable threshold detector allows moni-

toring the amplitude of the incoming signal with short latency,

using the four fast detect bits of the ADC. If the input signal level

exceeds the programmable threshold, the fine upper threshold

indicator goes high. Because this threshold is set from the four

MSBs, the user can quickly adjust the system gain to avoid an

overrange condition.

Another AGC-related function of the AD9600 is the signal

monitor. This block allows the user to monitor the composite

magnitude of the incoming signal, which aids in setting the gain

to optimize the dynamic range of the overall system.

The ADC output data can be routed directly to the two external

10-bit output ports. These outputs can be set from 1.8 V to 3.3 V

CMOS or 1.8 V LVDS. In addition, flexible power-down options

allow significant power savings.

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