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ADSP-21369BBP-2A Datasheet(PDF) 4 Page - Analog Devices |
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ADSP-21369BBP-2A Datasheet(HTML) 4 Page - Analog Devices |
4 / 60 page Rev. E | Page 4 of 60 | July 2009 ADSP-21367/ADSP-21368/ADSP-21369 The block diagram of the ADSP-21368 on Page 1 also shows the peripheral clock domain (also known as the I/O processor) and contains the following features: •IOD0 (peripheral DMA) and IOD1 (external port DMA) buses for 32-bit data transfers • Peripheral and external port buses for core connection • External port with an AMI and SDRAM controller •4 units for PWM control • 1 MTM unit for internal-to-internal memory transfers • Digital applications interface that includes four precision clock generators (PCG), a input data port (IDP) for serial and parallel interconnect, an S/PDIF receiver/transmitter, four asynchronous sample rate converters, eight serial ports, a flexible signal routing unit (DAI SRU). • Digital peripheral interface that includes three timers, a 2- wire interface, two UARTs, two serial peripheral interfaces (SPI), 2 precision clock generators (PCG) and a flexible sig- nal routing unit (DPI SRU). SHARC FAMILY CORE ARCHITECTURE The ADSP-21367/ADSP-21368/ADSP-21369 are code compati- ble at the assembly level with the ADSP-2126x, ADSP-21160, and ADSP-21161, and with the first generation ADSP-2106x SHARC processors. The ADSP-21367/ADSP-21368/ ADSP-21369 processors share architectural features with the ADSP-2126x and ADSP-2116x SIMD SHARC processors, as shown in Figure 2 and detailed in the following sections. Figure 2. SHARC Core Block Diadram S SIMD Core CACHE INTERRUPT 5 STAGE PROGRAM SEQUENCER PM ADDRESS 32 DM ADDRESS 32 DM DATA 64 PM DATA 64 DAG1 16x32 MRF 80-BIT ALU MULTIPLIER SHIFTER RF Rx/Fx PEx 16x40-BIT JTAG DMD/PMD 64 PM DATA 48 ASTATx STYKx ASTATy STYKy TIMER RF Sx/SFx PEy 16x40-BIT MRB 80-BIT MSB 80-BIT MSF 80-BIT FLAG SYSTEM I/F USTAT 4x32-BIT PX 64-BIT DAG2 16x32 ALU MULTIPLIER SHIFTER DATA SWAP PM ADDRESS 24 |
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