PCA9535ECDWR2G datasheet(9/20 Pages) ONSEMI

Part #	PCA9535ECDWR2G

Description	16-bit Low-Power I/O Expander for I2C Bus withInterrupt

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PCA9535E, PCA9535EC

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9

REGISTERS

Command Byte

During a write transmission, the address byte is followed

by the command byte. The command byte determines which

of the following registers will be written or read.

Table 7. COMMAND BYTE

COMMAND

REGISTER

0

Input Port 0

1

Input Port 1

2

Output Port 0

3

Output Port 1

4

Polarity Inversion Port 0

5

Polarity Inversion Port 1

6

Configuration Port 0

7

Configuration Port 1

Registers 0 and 1: Input Port Registers

These registers are input−only. They reflect the incoming

logic levels of the pins, regardless of whether the pin is

defined as an input or an output by Registers 6 or 7. Writes

to these registers have no effect.

The externally−applied logic level determines the default

value ‘X’.

Table 8. INPUT PORT 0 REGISTER

Bit

7

6

5

4

3

2

1

0

Symbol

I0.7

I0.6

I0.5

I0.4

I0.3

I0.2

I0.1

I0.0

Default

X

Table 9. INPUT PORT 1 REGISTER

Bit

7

6

5

4

3

2

1

0

Symbol

I1.7

I1.6

I1.5

I1.4

I1.3

I1.2

I1.1

I1.0

Default

X

Registers 2 and 3: Output Port Registers

These registers are output−only. They reflect the outgoing

logic levels of the pins defined as outputs by Registers 6 and

7. Bit values in these registers have no effect on pins defined

as inputs. In turn, reads from these registers reflect the values

that are in the flip−flops controlling the output selection, not

the actual pin values.

Table 10. OUTPUT PORT 0 REGISTER

Bit

7

6

5

4

3

2

1

0

Symbol

O0.7

O0.6

O0.5

O0.4

O0.3

O0.2

O0.1

O0.0

Default

1

Table 11. OUTPUT PORT 1 REGISTER

Bit

7

6

5

4

3

2

1

0

Symbol

O1.7

O1.6

O1.5

O1.4

O1.3

O1.2

O1.1

O1.0

Default

1

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