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SN65DSI96 Datasheet(PDF) 11 Page - Texas Instruments |
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SN65DSI96 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 68 page  R RST=150k VCCIO C EN SN65DSI86 C EN SN65DSI86 controller GPO Low Power (LP) Mode Receiver LP-RX Input LOW LP-RX Input HIGH 1.3V VIH-LP GND VIL-LP VIH-HS High Speed (HS) Mode Receiver HS-RX Common Mode Range VCM-HS(MAX) VCM-HS(MIN) VID VIL-HS SN65DSI86 SN65DSI96 www.ti.com SLLSEH2 – SEPTEMBER 2013 Figure 3. DSI Receiver Voltage Definitions RESET IMPLEMENTATION When EN is de-asserted, CMOS inputs are ignored, the MIPI® D-PHY inputs are disabled, and outputs are high impedance. It is critical to transition the EN input from a low to a high level after the VCC supply has reached the minimum recommended operating voltage. This is achieved by a control signal to the EN input, or by an external capacitor connected between EN and GND. To insure that the SN65DSIX6 is properly reset, the EN pin must be de-asserted for at least 100 µs before being asserted. When implementing the external capacitor, the size of the external capacitor depends on the power up ramp of the VCC supply, where a slower ramp-up results in a larger value external capacitor. Refer to the latest reference schematic for the SN65DSIX6 device and/or consider approximately 200nF capacitor as a reasonable first estimate for the size of the external capacitor. Both EN implementations are shown in the following figures. Figure 4. External Capacitor Controlled EN Figure 5. EN Input from Active Controller Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: SN65DSI86 SN65DSI96 |
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