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ADS1606IPAPTG4 Datasheet(PDF) 10 Page - Texas Instruments |
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ADS1606IPAPTG4 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 38 page  ADS1605 ADS1606 SBAS274H − MARCH 2003 − REVISED MAY 2007 www.ti.com 10 CLK DRDY DOUT[15:0] D1 D2 DL(2) t 2 t 2 t 16 t 17 t 21 t 15 t 20 t 18 t 19 t 1 t 13 t 14 CS(1) RD (1) CS may be tied low. (2) The number of data readings (DL) is set by the FIFO level. Figure 4. Data Retrieval Timing (ADS1606 with FIFO Enabled) RD, CS DOUT[15:0] t 8 t 7 Figure 5. DOUT Inactive/Active Timing (ADS1606 with FIFO Enabled) TIMING REQUIREMENTS FOR FIGURE 4 AND FIGURE 5 SYMBOL DESCRIPTION MIN TYP MAX UNIT t1 CLK period (1/fCLK) 20 25 1000 ns t2 CLK pulse width, high or low 10 ns t7 Rising edge of RD and/or CS inactive (high) to DOUT high impedance 7 15 ns t8 Falling edge of RD and/or CS active (low) to DOUT active. 7 15 ns t13 Rising edge of CLK to DRDY high 12 ns t14 DRDY period 8 × FIFO Level(1) CLK Cycles t15 DRDY positive pulse width 1 CLK Cycles t16 RD high hold time after DRDY goes low 0 ns t17 CS low before RD goes low 0 ns t18 RD negative pulse width 10 ns t19 RD positive pulse width 10 ns t20 RD high before DRDY toggles 2 CLK Cycles t21 RD high before CS goes high 0 ns NOTE: DOUT[15:0] and DRDY load = 10pF. (1) See FIFO section for more details. |
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