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ADS7817UC Datasheet(PDF) 11 Page - Texas Instruments |
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ADS7817UC Datasheet(HTML) 11 Page - Texas Instruments |
11 / 21 page ADS7817 11 SBAS066A D OUT 1.4V Test Point 3k Ω 100pF C LOAD t r D OUT V OH V OL t f t dDO t hDO D OUT DCLOCK V OH V OL V IL D OUT Test Point t dis Waveform 2, ten t dis Waveform 1 100pF C LOAD 3k Ω t dis CS/SHDN DOUT Waveform 1(1) DOUT Waveform 2(2) 90% 10% V IH 1 B11 2 t en CS/SHDN DCLOCK V OL D OUT V CC Load Circuit for tdDO, tr, and tf Voltage Waveforms for DOUT Rise and Fall Times tr, and tf Voltage Waveforms for DOUT Delay Times, tdDO Load Circuit for tdis and tden Voltage Waveforms for ten FIGURE 5. Timing Diagrams and Test Circuits for the Parameters in Table I. Voltage Waveforms for tdis NOTES: (1) Waveform 1 is for an output with internal conditions such that the output is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with internal conditions such that the output is LOW unless disabled by the output control. 1000 100 10 1 1 10 100 1000 Sample Rate (kHz) T A = 25°C V CC = +5V V REF = +2.5V f CLK = 3.2MHz FIGURE 6. Maintaining fCLK at the Highest Possible Rate Allows Supply Current to Drop Directly with Sample Rate. FIGURE 7. Scaling fCLK Reduces Supply Current Only Slightly with Sample Rate. 1000 100 10 1 1 10 100 1000 Sample Rate (kHz) T A = 25°C V CC = +5V V REF = +2.5V f CLK = 16 • fSAMPLE |
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