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BQ2204ASNTRG4 Datasheet(PDF) 1 Page - Texas Instruments |
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BQ2204ASNTRG4 Datasheet(HTML) 1 Page - Texas Instruments |
1 / 13 page Features ä Power monitoring and switching for 3-volt battery-backup applica- tions ä Write-protect control ä 2-input decoder for control of up to 4 banks of SRAM ä 3-volt primary cell inputs ä Less than 10ns chip-enable propagation delay ä 5% or 10% supply operation General Description The CMOS bq2204A SRAM Non- volatile Controller Unit provides all necessary functions for converting up to four banks of standard CMOS SRAM into nonvolatile read/write memory. A precision comparator monitors the 5V VCC input for an out-of-tolerance condi- tion. When out-of-tolerance is detected, the four conditioned chip-enable outputs are forced inactive to write-protect up to four banks of SRAM. During a power failure, the external SRAMs are switched from the VCC supply to one of two 3V backup sup- plies. On a subsequent power-up, the SRAMs are write-protected until a power-valid condition exists. During power-valid operation, a two-input decoder transparently se- lects one of up to four banks of SRAM. 1 Dec. 1992 B bq2204A X4 SRAM Nonvolatile Controller Unit 1 PN220401.eps 16-Pin Narrow DIP or SOIC 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC BC1 CE CECON1 CECON2 CECON3 CECON4 NC VOUT BC2 NC A B NC THS VSS Pin Names VOUT Supply output BC1–BC2 3 volt primary backup cell inputs THS Threshold select input CE chip-enable active low input CECON1– Conditioned chip-enable outputs CECON4 A–B Decoder inputs NC No connect VCC +5 volt supply input VSS Ground Up to four banks of CMOS static RAM can be battery- backed using the VOUT and conditioned chip-enable out- put pins from the bq2204A. As VCC slews down during a power failure, the conditioned chip-enable outputs CECON1 through CECON4 are forced inactive independ- ent of the chip-enable input CE. This activity unconditionally write-protects the external SRAM as VCC falls below an out-of-tolerance threshold VPFD.VPFD is selected by the threshold select input pin, THS. If THS is tied to VSS, the power-fail detection occurs at 4.62V typical for 5% supply operation. If THS is tied to VCC, power-fail detection occurs at 4.37V typical for 10% supply operation. The THS pin must be tied to VSS or VCC for proper operation. If a memory access is in process to any of the four external banks of SRAM during power-fail detection, that memory cycle continues to completion before the memory is write- protected. If the memory cycle is not terminated within time tWPT, all four chip-enable outputs are unconditionally driven high, write-protecting the controlled SRAMs. Pin Connections Functional Description |
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