DS90LV028A

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SNLS013E – JUNE 1998 – REVISED APRIL 2013

APPLICATION INFORMATION

General application guidelines and hints for LVDS drivers and receivers may be found in the following application

notes: LVDS Owner's Manual (SNLA187), AN-808 (SNLA028), AN-977 (SNLA166), AN-971 (SNLA165), AN-916

(SNLA219), AN-805 (SNOA233), AN-903 (SNLA034).

LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as

is shown in Figure 5. This configuration provides a clean signaling environment for the fast edge rates of the

drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair

cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the

range of 100

Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to

the receiver input pins as possible. The termination resistor converts the driver output (current mode) into a

voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration,

but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as

ground shifting, noise margin limits, and total termination loading must be taken into account.

The DS90LV028A differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V

common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V.

The driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting

may be the result of a ground potential difference between the driver's ground reference and the receiver's

ground reference, the common-mode effects of coupled noise, or a combination of the two. The AC parameters

of both receiver input pins are optimized for a recommended operating input voltage range of 0V to +2.4V

POWER DECOUPLING RECOMMENDATIONS

Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended)

0.1

μF and 0.01μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the

device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple

vias should be used to connect the decoupling capacitors to the power planes. A 10

μF (35V) or greater solid

tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply

and ground.

PC BOARD CONSIDERATIONS

Use at least 4 PCB board layers (top to bottom): LVDS signals, ground, power, TTL signals.

Isolate TTL signals from LVDS signals, otherwise the TTL signals may couple onto the LVDS lines. It is best to

put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s).

Keep drivers and receivers as close to the (LVDS port side) connectors as possible.

For PC board considerations for the WSON package, please refer to application note AN-1187 “Leadless

Leadframe Package” (SNOA401) It is important to note that to optimize signal integrity (minimize jitter and noise

coupling), the WSON thermal land pad, which is a metal (normally copper) rectangular region located under the

package as seen in Figure 6, should be attached to ground and match the dimensions of the exposed pad on the

PCB (1:1 ratio).

Figure 6. WSON Thermal Land Pad and Pin Pads

Copyright © 1998–2013, Texas Instruments Incorporated

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