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ISO7420FED Datasheet(PDF) 11 Page - Texas Instruments

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Part # ISO7420FED
Description  Low-Power Dual Channel Digital Isolators
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

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Case Temperature − C
°
0
20
40
60
80
100
120
140
160
180
0
50
100
150
200
VCC1, VCC2 at 3.6 V
VCC1, VCC2 at 5.5 V
ISO7420E, ISO7420FE
ISO7421E, ISO7421FE
www.ti.com
SLLSE45E – DECEMBER 2010 – REVISED JANUARY 2013
IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of
the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat
the die and damage the isolation barrier, potentially leading to secondary system failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
θJA = 212°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C
107
Safety input, output, or supply
IS
mA
current
θJA = 212°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C
164
TS
Maximum case temperature
150
°C
The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum
Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Characteristics table is that of a device installed in the JESD51-3, Low-Effective-Thermal-Conductivity
Test Board for Leaded Surface-Mount Packages and is conservative. The power is the recommended maximum
input voltage times the current. The junction temperature is then the ambient temperature plus the power times
the junction-to-air thermal resistance.
PACKAGE THERMAL CHARACTERISTICS
(over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Low-K thermal resistance(1)
212
θJA
Junction-to-air thermal resistance
°C/W
High-K thermal resistance(1)
122
θJB
Junction-to-board thermal resistance
37
°C/W
θJC
Junction-to-case thermal resistance
69.1
°C/W
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
PD
Device power dissipation
138
mW
Input a 100-Mbps 50% duty-cycle square wave
(1)
Tested in accordance with the low-K or high-K thermal metric definitions of EIA/JESD51-3 for leaded surface-mount packages
Figure 5.
θJC Thermal Derating Curve per IEC 60747-5-2
Copyright © 2010–2013, Texas Instruments Incorporated
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Product Folder Links: ISO7420E ISO7420FE ISO7421E ISO7421FE


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