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SN65LVDS96DGGG4 Datasheet(PDF) 5 Page - Texas Instruments |
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SN65LVDS96DGGG4 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 17 page www.ti.com at clock periods other than 15.38 ns can be calculated from tc 14 –600 ps. ELECTRICAL CHARACTERISTICS SWITCHING CHARACTERISTICS SN65LVDS96 SLLS296H – MAY 1998 – REVISED JULY 2006 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VIT+ Positive-going differential Input voltage threshold 100 mV VIT- Negative-going differential Input voltage threshold(2) –100 mV VOH High-level output voltage IOH = –4 mA 2.4 V VOL Low-level output voltage IOH = 4 mA 0.4 V Disabled, all inputs open 280 µA Enabled, AnP at 1 V and AnM at 1.4 V, 60 82 ICC Quiescent current (average) tc = 15.38 ns mA Enabled, CL = 8 pF, Worst-case pattern 94 (see Figure 4), tc = 15.38 ns IIH High-level input current (SHTDN) VIH = VCC ±20 µA IIL Low-level input current (SHTDN) VIL = 0 V ±20 µA IIN Input current (A inputs) 0 V ≤ V I ≤ 2.4 V ±20 µA IOZ High-impedance output current VO = 0 V to VCC ±10 µA (1) All typical values are VCC = 3.3 V, TA = 25°C. (2) The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the negative-going input voltage threshold only. over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tsu Data setup time, D0 through D20 to CLKOUT ↑ 3.4 6 CL = 8 pF, See Figure 5 ns th Data hold time, CLKOUT ↑ to D0 through D20 4 6 TA = 0°C to 85°C 490 800 ps Receiver input skew margin(1) tc = 15.38 ns (±0.2%), tRSKM (see Figure 7) |Input clock jitter| <50 ps(2) TA = –40°C to 0°C 350 ps Delay time, input clock to output clock td tc = 15.38 ns (±0.2%) 3.7 ns (see Figure 7) tc = 15.38 + 0.75 sin (2π500E3t) ±0.05 ns, ±80 See Figure 7 Change in output clock period from ∆t C(O) ps cycle to cycle(3) tc = 15.38 + 0.75 sin (2π3E6t) ±0.05 ns, ±300 See Figure 7 ten Enable time, SHTDN to phase lock See Figure 8 1 ms tdis Disable time, SHTDN to Off state See Figure 9 400 ns tt Output transition time (10% to 90% tr or tf) CL = 8 pF 3 ns tw Output clock pulse duration 0.43 tc ns (1) tRSKM is the timing margin available to allocate to the transmitter and interconnection skews and clock jitter. The value of this parameter (2) |Input clock jitter| is the magnitude of the change in the input clock period. (3) ∆t C(O) is the change in the output clock period from one cycle to the next cycle observed over 15,000 cycles. 5 Submit Documentation Feedback |
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