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at clock periods other than 15.38 ns can be calculated from

tc

14

–600 ps.

ELECTRICAL CHARACTERISTICS

SWITCHING CHARACTERISTICS

SN65LVDS96

SLLS296H – MAY 1998 – REVISED JULY 2006

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

UNIT

Positive-going differential Input voltage threshold

100

mV

–100

mV

High-level output voltage

2.4

V

Low-level output voltage

0.4

V

Disabled, all inputs open

280

µA

Enabled, AnP at 1 V and AnM at 1.4 V,

60

82

Quiescent current (average)

mA

94

High-level input current (SHTDN)

±20

µA

Low-level input current (SHTDN)

±20

µA

Input current (A inputs)

0 V

≤ V

±20

µA

High-impedance output current

±10

µA

(1)

(2)

The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the

negative-going input voltage threshold only.

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX

UNIT

Data setup time, D0 through D20 to CLKOUT

↑

3.4

6

See Figure 5

ns

Data hold time, CLKOUT

↑ to D0 through D20

4

6

490

800

ps

(see Figure 7)

350

ps

Delay time, input clock to output clock

3.7

ns

(see Figure 7)

±80

See Figure 7

Change in output clock period from

∆t

C(O)

ps

±300

See Figure 7

Enable time, SHTDN to phase lock

See Figure 8

1

ms

Disable time, SHTDN to Off state

See Figure 9

400

ns

3

ns

Output clock pulse duration

ns

(1)

(2)

|Input clock jitter| is the magnitude of the change in the input clock period.

(3)

∆t

5

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