TPS5130

SLVS426 − MAY 2002

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11

OVER CURRENT PROTECTION

Over current protection (OCP) is achieved by comparing the drain-to-source voltage of the high-side and low-side MOSFET

voltage exceeds the set-point voltage during low-side conduction, the high-side current comparator becomes active, and

the low-side pulse is extended until this voltage comes back below the threshold. If the set-point voltage is exceeded during

high-side conduction in the following cycle, the current limit circuit terminates the high-side driver pulse. Together this action

has the effect of decreasing the output voltage until the under voltage protection circuit is activated to latch both the

order to compensate for temperature drift of the MOSFET on-resistance.

OCP FOR THE LDO

To achieve the LDO current limit, a sense resistor must be placed in series with the N-channel MOSFET drain, connected

between the LDO_IN and LDO_CUR pins (see reference schematic). If the voltage drop across this sense resistor exceeds

50 mV, the output voltage is reduced to approximately 22% of the nominal value, thus it activates the UVP to start the FLT

latch timer. When the time is up, the LDO_GATE pin is pulled LOW to makes the LDO regulator shut down. Note that all

of the SBRCs are latched OFF at the same time since the LDO and the SBRCs share the same FLT capacitor.

OVER VOLTAGE PROTECTION

For overvoltage protection (OVP), the TPS5130 monitors the INVx and INV_LDO pin voltages. When the INVx or INV_LDO

pin voltage is higher than 0.95 V (0.85 V +12%), the OVP comparator output goes low and the FLT timer starts to charge

an external capacitor connected to FLT pin. After a set time, the FLT circuit latches the high-side MOSFET driver, the

low-side MOSFET drivers, and the LDO. The latched state of each block is summarized in Table 2. The timer source current

for the OVP latch is 125

µA(typ.), and the time-up voltage is 1.185 V (typ.). The OVP timer is designed to be 50 times faster

than the under voltage protection timer described in Table 2.

Table 2. OVP Logic

OVP OCCURRED AT

HIGH-SIDE MOSFET DRIVER

LOW-SIDE MOSFET DRIVER

LDO

SBRC

OFF

ON

OFF

LDO

OFF

OFF

OFF

UNDER VOLTAGE PROTECTION

For under voltage protection (UVP), the TPS5130 monitors the INVx and INV_LDO pin voltages. When the INVx or

INV_LDO pin voltage is lower than 0.55 V (0.85 V - 35 %), the UVP comparator output goes low, and the FLT timer starts

to charge the external capacitor connected to FLT pin. Also, when the current comparator triggers the OCP, the UVP

comparator detects the under voltage output and starts the FLT capacitor charge, too. After a set time, the FLT circuit latches

all of the MOSFET drivers to the OFF state. The timer latch source current for UVP is 2.3

µA (typ.), and the time-up voltage

is also 1.185 V (typ.). The UVP function of the LDO controller is disabled when voltage across the pass transistor is less

than 0.23 V (typ.).

FLT

When an OVP or UVP comparator output goes low, the FLT circuit starts to charge the FLT capacitor. If the FLT pin voltage

goes beyond a constant level, the TPS5130 latches the MOSFET drivers. At this time, the state of MOSFET is different

depending on the OVP alert and the UVP alert (see Table 2). The enable time used to latch the MOSFET drivers is decided

by the value of the FLT capacitor. The charging constant current value depends on whether it is an OVP alert or a UVP

alert as shown in the following equation:

FLT source current (OVP) = FLT source current (UVP)

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