1.8V, Low-Power, 12-Bit, 250Msps

ADC for Broadband Applications

8

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Pin Description

PIN

NAME

FUNCTION

1, 6, 11–14, 20,

25, 62, 63, 65

Bypassing, and Layout Considerations section.

2, 5, 7, 10, 15, 16,

18, 19, 21, 24,

64, 66, 67

AGND

Analog Converter Ground. Connect all AGND inputs together.

3

REFIO

Reference Input/Output. Pull REFADJ high to allow REFIO to accept an external reference. Pull

REFADJ low to activate the internal 1.25V-bandgap reference. Connect a 0.1µF capacitor from

REFIO to AGND for both internal and external reference.

4

REFADJ

Reference Adjust Input. REFADJ allows for FSR adjustments by placing a resistor or trim

potentiometer between REFADJ and AGND (decreases FSR) or REFADJ and REFIO (increases

connected to REFIO. Connect REFADJ to AGND to allow the internal reference to determine the

FSR of the data converter. See the FSR Adjustment Using the Internal Reference section.

8

INP

Positive Analog Input Terminal. Internally self-biased to 0.7V.

9

INN

Negative Analog Input Terminal. Internally self-biased to 0.7V.

17

CLKDIV

Clock Divider Input. CLKDIV controls the sampling frequency relative to the input clock

frequency. CLKDIV has an internal pulldown resistor.

CLKDIV = 0: Sampling frequency is at one-half the input clock frequency.

CLKDIV = 1: Sampling frequency is equal to the input clock frequency.

22

CLKP

True Clock Input. Apply an LVDS-compatible input level to CLKP. Internally self-biased to 1.15V.

23

CLKN

Complementary Clock Input. Apply an LVDS-compatible input level to CLKN. Internally self-

biased to 1.15V.

26, 45, 61

OGND

Digital Converter Ground. Ground connection for digital circuitry and output drivers. Connect all

OGND inputs together.

27, 28, 41, 44, 60

together. See the Grounding, Bypassing, and Layout Considerations section.

29

D0N

Complementary Output Bit 0 (LSB)

30

D0P

True Output Bit 0 (LSB)

31

D1N

Complementary Output Bit 1

32

D1P

True Output Bit 1

33

D2N

Complementary Output Bit 2

34

D2P

True Output Bit 2

35

D3N

Complementary Output Bit 3

36

D3P

True Output Bit 3