1.8V, Low-Power, 12-Bit, 170Msps

ADC for Broadband Applications

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9

Pin Description (continued)

PIN

NAME

FUNCTION

37

D4N

Complementary Output Bit 4

38

D4P

True Output Bit 4

39

D5N

Complementary Output Bit 5

40

D5P

True Output Bit 5

42

DCLKN

Complementary Clock Output. This output provides an LVDS-compatible output level and can

be used to synchronize external devices to the converter clock.

43

DCLKP

True Clock Output. This output provides an LVDS-compatible output level and can be used to

synchronize external devices to the converter clock.

46

D6N

Complementary Output Bit 6

47

D6P

True Output Bit 6

48

D7N

Complementary Output Bit 7

49

D7P

True Output Bit 7

50

D8N

Complementary Output Bit 8

51

D8P

True Output Bit 8

52

D9N

Complementary Output Bit 9

53

D9P

True Output Bit 9

54

D10N

Complementary Output Bit 10

55

D10P

True Output Bit 10

56

D11N

Complementary Output Bit 11 (MSB)

57

D11P

True Output Bit 11 (MSB)

58

ORN

Complementary Out-of-Range Control Bit Output. If an out-of-range condition is detected,

bit ORN flags this condition by transitioning low.

59

ORP

True Out-of-Range Control Bit Output. If an out-of-range condition is detected, bit ORP flags

this condition by transitioning high.

68

T/B

Output Format Select. This LVCMOS-compatible input controls the digital output format of the

MAX1213N. T/B has an internal pulldown resistor.

T/B = 0: Two’s-complement output format.

T/B = 1: Binary output format.

—EP

Exposed Paddle. The exposed paddle is located on the backside of the chip and must be

connected to AGND.