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MAX1214N Datasheet(PDF) 4 Page - Maxim Integrated Products |
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MAX1214N Datasheet(HTML) 4 Page - Maxim Integrated Products |
4 / 21 page 1.8V, Low-Power, 12-Bit, 250Msps ADC for Broadband Applications 4 ________________________________________________________________________________________ ELECTRICAL CHARACTERISTICS (continued) (AVCC = OVCC = 1.8V, AGND = OGND = 0, fSAMPLE = 250MHz, differential clock input drive, 0.1µF capacitor on REFIO, internal ref- erence, digital output pins differential RL = 100Ω. Limits are for TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVCMOS DIGITAL INPUTS (CLKDIV, T/B) Digital Input-Voltage Low VIL 0.2 x AVCC V Digital Input-Voltage High VIH 0.8 x AVCC V TIMING CHARACTERISTICS CLK-to-Data Propagation Delay tPDL Figure 5 2.23 ns CLK-to-DCLK Propagation Delay tCPDL Figure 5 3.77 ns DCLK-to-Data Propagation Delay tCPDL - tPDL Figure 5 (Note 3) 1.47 1.54 1.63 ns LVDS Output Rise Time tRISE 20% to 80%, CL = 5pF 155 ps LVDS Output Fall Time tFALL 20% to 80%, CL = 5pF 145 ps Output Data Pipeline Delay tLATENCY Figure 5 11 Clock cycles POWER REQUIREMENTS Analog Supply Voltage Range AVCC 1.7 1.8 1.9 V Digital Supply Voltage Range OVCC 1.7 1.8 1.9 V Analog Supply Current IAVCC fIN = 100MHz 428 480 mA Digital Supply Current IOVCC fIN = 100MHz 64 74 mA Analog Power Dissipation PDISS fIN = 100MHz 886 965 mW Offset 1.7 mV/V Power-Supply Rejection Ratio (Note 4) PSRR Gain 4.5 %FS/V Note 1: TA ≥ +25°C guaranteed by production test, TA < +25°C guaranteed by design and characterization. Typical values are at TA = +25°C Note 2: Static linearity and offset parameters are computed from an endpoint curve fit. Note 3: Parameter guaranteed by design and characterization: TA = -40°C to +85°C. Note 4: PSRR is measured with both analog and digital supplies connected to the same potential. |
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