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AT49BV008AT-90CI Datasheet(PDF) 5 Page - ATMEL Corporation |
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AT49BV008AT-90CI Datasheet(HTML) 5 Page - ATMEL Corporation |
5 / 16 page AT49BV008A(T)/8192A(T) 5 hardware operation mode can be used by an external pro- grammer to identify the correct programming algorithm for the Atmel product. For details, see “Operating Modes” on page 8 (for hard- ware operation) or “Software Product Identification Entry/Exit” on page 13. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49BV008A(T)/8192A(T) features Data Polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the program or erase cycle has completed, true data will be read from the device. Data Polling may begin at any time during the program cycle. TOG G LE BI T: I n a ddit i on to Da ta Pollin g, the AT49BV008A(T)/8192A(T) provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. READY/BUSY: For the AT49BV008A(T), pin 12 is an open-drain Ready/Busy output pin that provides another method of detecting the end of a program or erase opera- tion. RDY/BUSY is actively pulled low during the internal program and erase cycles and it is released at the comple- tion of the cycle. The open-drain connection allows for OR- tying of several devices to the same RDY/BUSY line. HARDWARE DATA PROTECTION: Hardware features pr ot ect ag ainst ina d ver t e n t pr og r a ms t o the AT49BV008A(T)/8192A(T) in the following ways: (a) VCC sense: if V CC is below 1.8V (typical), the program function is inhibited. (b) V CC power on delay: once VCC has reached the V CC sense level, the device will automatically time-out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to V CC + 0.6V. AT49BV008A(T) ALTERNATE PIN DEFINITION: Two AT49BV008A(T) BGA pin definitions are shown. The stan- dard pin definition allows use of the JEDEC standard pro- gramming algorithm. If the alternate pin definition is used, the programming algorithm must be modified as shown in the Command Definition for Alternate Pin Definition table on page 7. |
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